Parallel chaos-based image encryption algorithm: high-level synthesis and FPGA implementation

Nowadays, establishing security in data transmission is essential, and it is achieved by cryptography. Encryption of still or video images in specific applications such as Internet of Things, medical and satellite imaging, in applications requiring high-speed encryption, or even in applications where a personal computer is unavailable or cannot be used needs special hardware. In this paper, an image encryption algorithm based on chaos theory named Parallel Chaotic Checksum-based Image Encryption or PCCIE algorithm is proposed that has been able to provide a fast, efficient and secure algorithm with a hardware perspective on the design and parallel system structure. Using high-level synthesis, PCCIE is implemented on a Field Programmable Gate Array (FPGA). The proposed algorithm using small and independent local image buffers solved FPGA internal memory limitation for encryption of large images. Ultimately, a Hexa-core crypto-processor with single-precision floating-point and fixed-point precision has been designed, capable of encrypting 256 × 256 and Full HD images in 2.13 and 59.52 milliseconds, respectively, at 469 and 16 frames per second.