Online Condition Monitoring for GaN Power Devices With Integrated Dynamic On-Resistance Full Profile Scan and Offset Calibration
Emerging GaN high electron mobility transistors have become a popular choice in high-efficiency, high-speed power circuits, owing to superb switching figure of merits. However, as a new type of power devices, aging/failure mechanisms of such are far less studied than silicon counterparts, making rel...
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Veröffentlicht in: | IEEE transactions on power electronics 2024-05, Vol.39 (5), p.6215-6224 |
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Sprache: | eng |
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Zusammenfassung: | Emerging GaN high electron mobility transistors have become a popular choice in high-efficiency, high-speed power circuits, owing to superb switching figure of merits. However, as a new type of power devices, aging/failure mechanisms of such are far less studied than silicon counterparts, making reliability one of the most formidable obstacles towards mass production. To mitigate this, device online condition monitoring is highly desirable, in which dynamic on-resistance, dR ON , is popularly employed as an aging precursor. However, continuous and drastic changes of operation condition and switching dynamics make it highly challenging to measure dR ON online accurately. To address such, this article introduces an integrated dR ON full profile scan and offset calibration approach that allows GaN power devices to be monitored online without interrupting normal operation of device under test (DUT), making it a desirable plug-and-play solution to virtually all GaN-based power circuits. To facilitate superior speed and low-power performance, this article is implemented on a highly silicon- and power-efficient integrated circuit, which calibrates random offsets and sensing errors automatically to ensure condition monitoring accuracy. Demonstrated in a half-bridge GaN-based power converter, where the gate drivers and the feedback controller are fully integrated on a 180-nm high voltage bipolar-CMOS-DMOS (BCD) process, the proposed online condition monitoring solution consumes only 1.1 mW power and 0.3 mm 2 chip area, which account for 0.077% power and 4.8% chip overhead, respectively. It reduces offset and parasitic induced sensing errors by 13.6%. |
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ISSN: | 0885-8993 1941-0107 |
DOI: | 10.1109/TPEL.2024.3352181 |