Analysis of Stochastic Phase-Frequency Detector in 2x Oversampling Clock and Data Recovery

This brief presents an analysis of a stochastic phase-frequency detector (SPFD) in 2x oversampling clock and data recovery (CDR) circuits. First, we analyze the operating conditions required for a phase detector (PD) and suggest possible solutions beyond the typical bang-bang PD (BBPD). In the same manner, the required conditions and feasible weight sets of a PFD for a 2x oversampling CDR are obtained. The simulated PD and FD gain curves are shown to validate the analysis and compare the solutions. Lastly, we demonstrate the performance tradeoff between frequency locking transient and jitter tolerance in the 2x oversampling CDR with respect to the PFD weight sets through a behavioral simulation based on SystemVerilog.