Analysis of the Role of Interfacial Layer in Ferroelectric FET Failure as a Memory Cell
By observing temporary and permanent changes in threshold voltage ( {V}_{\text {T}} ) due to the application of unipolar/bipolar stress, it was confirmed that the trap-carrier interaction speed is the cause of failure of the ferroelectric transistor as a memory. As the polarization switching occurs,...
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| Veröffentlicht in: | IEEE electron device letters 2024-04, Vol.45 (4), p.562-565 |
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| creator | Lee, Seongwon Kim, Haesung Yang, Hyojin Yun, Sanghyuk Park, Junseong Lee, Haneul Park, Sejun Choi, Sung-Jin Kim, Dae Hwan Kim, Dong Myong Kwon, Daewoong Bae, Jong-Ho |
| description | By observing temporary and permanent changes in threshold voltage ( {V}_{\text {T}} ) due to the application of unipolar/bipolar stress, it was confirmed that the trap-carrier interaction speed is the cause of failure of the ferroelectric transistor as a memory. As the polarization switching occurs, carriers are trapped in the ferroelectric/interfacial layer (FE/IL), and the hole trap is limited compared to the electron trap due to the slow interaction. IL degrades under bipolar stress due to the high electric field during polarization switching, leading to the acceleration of hole trapping, which has a strong impact on the memory window. |
| doi_str_mv | 10.1109/LED.2024.3360419 |
| format | Article |
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As the polarization switching occurs, carriers are trapped in the ferroelectric/interfacial layer (FE/IL), and the hole trap is limited compared to the electron trap due to the slow interaction. IL degrades under bipolar stress due to the high electric field during polarization switching, leading to the acceleration of hole trapping, which has a strong impact on the memory window.</description><identifier>ISSN: 0741-3106</identifier><identifier>EISSN: 1558-0563</identifier><identifier>DOI: 10.1109/LED.2024.3360419</identifier><identifier>CODEN: EDLEDZ</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Acceleration ; Degradation ; Electric fields ; FeFETs ; Ferroelectric ; Ferroelectric materials ; Ferroelectricity ; Field effect transistors ; Hafnium oxide ; hole trapping ; Hole traps ; Iron ; Polarization ; Silicon ; Stress ; Switches ; Switching ; Threshold voltage</subject><ispartof>IEEE electron device letters, 2024-04, Vol.45 (4), p.562-565</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. 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As the polarization switching occurs, carriers are trapped in the ferroelectric/interfacial layer (FE/IL), and the hole trap is limited compared to the electron trap due to the slow interaction. IL degrades under bipolar stress due to the high electric field during polarization switching, leading to the acceleration of hole trapping, which has a strong impact on the memory window.</description><subject>Acceleration</subject><subject>Degradation</subject><subject>Electric fields</subject><subject>FeFETs</subject><subject>Ferroelectric</subject><subject>Ferroelectric materials</subject><subject>Ferroelectricity</subject><subject>Field effect transistors</subject><subject>Hafnium oxide</subject><subject>hole trapping</subject><subject>Hole traps</subject><subject>Iron</subject><subject>Polarization</subject><subject>Silicon</subject><subject>Stress</subject><subject>Switches</subject><subject>Switching</subject><subject>Threshold voltage</subject><issn>0741-3106</issn><issn>1558-0563</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2024</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNpNkD1PwzAURS0EEqWwMzBYYk7xS_yVsSotVApCQiBGy3WeRSq3KXY65N-TqB2Y3h3OvdI7hNwDmwGw8qlaPs9ylvNZUUjGobwgExBCZ0zI4pJMmOKQFcDkNblJacsYcK74hHzP9zb0qUm09bT7QfrRBhzzet9h9NY1NtDK9hhps6crjLHFgK6LjaOr5Sdd2SYcI1KbqKVvuGtjTxcYwi258jYkvDvfKfka8MVrVr2_rBfzKnM5F11Wc7Ba6tp6RMv4RnrvgSvlYCNrq7WQG-5KnSusnfTovFJaiVrUlqkCLBRT8njaPcT294ipM9v2GIefksnLUoDIpR4pdqJcbFOK6M0hNjsbewPMjPrMoM-M-sxZ31B5OFUaRPyHc9AgoPgDCLxq0A</recordid><startdate>20240401</startdate><enddate>20240401</enddate><creator>Lee, Seongwon</creator><creator>Kim, Haesung</creator><creator>Yang, Hyojin</creator><creator>Yun, Sanghyuk</creator><creator>Park, Junseong</creator><creator>Lee, Haneul</creator><creator>Park, Sejun</creator><creator>Choi, Sung-Jin</creator><creator>Kim, Dae Hwan</creator><creator>Kim, Dong Myong</creator><creator>Kwon, Daewoong</creator><creator>Bae, Jong-Ho</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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As the polarization switching occurs, carriers are trapped in the ferroelectric/interfacial layer (FE/IL), and the hole trap is limited compared to the electron trap due to the slow interaction. IL degrades under bipolar stress due to the high electric field during polarization switching, leading to the acceleration of hole trapping, which has a strong impact on the memory window.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/LED.2024.3360419</doi><tpages>4</tpages><orcidid>https://orcid.org/0000-0002-3392-9444</orcidid><orcidid>https://orcid.org/0009-0005-9323-984X</orcidid><orcidid>https://orcid.org/0000-0003-1301-2847</orcidid><orcidid>https://orcid.org/0000-0002-1786-7132</orcidid><orcidid>https://orcid.org/0000-0002-0858-5854</orcidid><orcidid>https://orcid.org/0000-0003-2567-4012</orcidid></addata></record> |
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| subjects | Acceleration Degradation Electric fields FeFETs Ferroelectric Ferroelectric materials Ferroelectricity Field effect transistors Hafnium oxide hole trapping Hole traps Iron Polarization Silicon Stress Switches Switching Threshold voltage |
| title | Analysis of the Role of Interfacial Layer in Ferroelectric FET Failure as a Memory Cell |
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