High-speed low power energy efficient 1- trit multiplier with less number of CNTFETs

Ternary logic has an advantage over conventional binary logic since it uses less power and promises to take up less space on chips and in interconnects. When ternary logic is used to design multiplier circuits, they exhibit good efficiency. A device known as a carbon nanotube field-effect transistor (CNTFET) offers more benefits than a MOSFET, including low off-current characteristics like low power and good performance. In this paper, a new 1-trit multiplier design is suggested along with a comparison of four 1-trit multiplier ideas based on CNTFETs. Power, latency, PDP, and the number of transistors is compared. Power, speed, and PDP are all improved by the suggested 1-trit multiplier. There are fewer transistors required. The Cadence Virtuoso Tool simulates each of these circuits using CNTFET 32 nm technology.