ASC: Adaptive Scale Feature Map Compression for Deep Neural Network

Deep-learning accelerators are increasingly in demand; however, their performance is constrained by the size of the feature map, leading to high bandwidth requirements and large buffer sizes. We propose an adaptive scale feature map compression technique leveraging the unique properties of the featu...

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Veröffentlicht in:IEEE transactions on circuits and systems. I, Regular papers Regular papers, 2024-03, Vol.71 (3), p.1417-1428
Hauptverfasser: Yao, Yuan, Chang, Tian-Sheuan
Format: Artikel
Sprache:eng
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Zusammenfassung:Deep-learning accelerators are increasingly in demand; however, their performance is constrained by the size of the feature map, leading to high bandwidth requirements and large buffer sizes. We propose an adaptive scale feature map compression technique leveraging the unique properties of the feature map. This technique adopts independent channel indexing given the weak channel correlation and utilizes a cubical-like block shape to benefit from strong local correlations. The method further optimizes compression using a switchable endpoint mode and adaptive scale interpolation to handle unimodal data distributions, both with and without outliers. This results in 4\times and up to 7.69\times compression rates for 16-bit data in constant and variable bitrates, respectively. Our hardware design minimizes area cost by adjusting interpolation scales, which facilitates hardware sharing among interpolation points. Additionally, we introduce a threshold concept for straightforward interpolation, preventing the need for intricate hardware. The TSMC 28nm implementation showcases an equivalent gate count of 6135 for the 8-bit version. Furthermore, the hardware architecture scales effectively, with only a sublinear increase in area cost. Achieving a 32\times throughput increase meets the theoretical bandwidth of DDR5-6400 at just 7.65\times the hardware cost.
ISSN:1549-8328
1558-0806
DOI:10.1109/TCSI.2023.3337283