Improved DC Performances of Gate-all-around Si-Nanotube Tunnel FETs Using Gate-Source Overlap

In this work, a novel structure of Gate-all-Around Si-Nanotube Tunnel FET (GAA Si-NTTFET) has been proposed to improve its electrical characteristics by overlapping a portion of source with its gate terminal. Using 3-D TCAD simulation, it has been found that the on-state current and subthreshold swing of GAA Si-NTTFET can be significantly improved with an optimum length of gate-source overlapping (GSO) i.e. 27-nm only, thus not limiting the scalability of source region. Furthermore, GSO has also caused a reduction in the turn-on voltage of GAA Si-NTTFET which may help to scaling the supply voltages. Moreover, due to reduction in the lateral electric field at source-channel interface caused by GSO, the off-state current has been observed to be smaller as compared to the conventional GAA Si-NTTFET which eventually reduces the stand-by power dissipation. Additionally, the ambipolar current has also been found to be reduced in the proposed structure which makes it more suitable for its application in the digital circuits.