A Novel Nanoscale SOI MOSFET by Using a P-N Junction and an Electrically Hole Free Region to Improve the Electrical Characteristics

In this paper, a SOI MOSFET is proposed using a P-N structure and an electrically hole-free region (EHFR-SOI). In this structure, to improve the electrical characteristics such as short channel effects, self-heating effects, and floating body effects, a Si 3 N 4 layer is used on the source side of the SOI MOSFET with a P-N structure. The proposed technique converts the P-N structure to a N-P-N structure by creating an electrically hole-free region. So, by reducing the applied electric field to the carriers, a significant reduction in the electron temperature of the device will be created. Simulations and studies of the structure show that its thermal behavior is significantly improved. Also, the floating body effect, effective mobility, hot electron effect, and electric field in the structure are enhanced compared to a conventional SOI (C-SOI) structure. In addition, the gate-source and gate-drain capacitors have been improved, which indicates a higher switching speed of the structure.