Design and Temperature Assessment of Junctionless Nanosheet FET for Nanoscale Applications

Nanosheets are the revolutionary change to overcome the limitations of FinFET. In this paper, the temperature dependence of 10 nm junctionless (JL) nanosheet FET performance on DC and analog/RF characteristics are investigated for the first time using extended source/drain and with high- k gate stack. The detailed DC performance analysis like transfer characteristics ( I D - V GS ), output characteristics ( I D - V DS ), drain induced barrier lowering (DIBL), subthreshold swing (SS) and I ON / I OFF ratio are evaluated from 200 K to 350 K. We also analyzed the temperature effect on the ON-OFF performance metric (Q), dynamic power, and power consumption. Furthermore, to understand the device performance on various process parameters like doping and work function variations are presented at 300 K. The proposed device exhibits good I ON / I OFF switching behavior with I OFF reaching less than nA for all temperatures. The cutoff frequency ( f T ) is determined to be in the THz range the Q ranges between 1.5 to 2.2 μS-dec/mV for temperatures between 200 K to 350 K at L G of 10 nm. Moreover, the scaling effect of nanosheet at various gate lengths ( L G = 5 to 20 nm) are also presented. From simulation analysis we notice that analog/RF performance parameters of a JL nanosheet FET are less sensitive to temperature variations. At extremely scaled L G the JL nanosheet FET exhibits lesser power consumption, power and decreases with increase in temperature. Thus, the proposed JL nanosheet FET demonstrates as a strong potential contender for low power and high frequency applications at nano-regime.