Comparison and extension of high performance adders for hybrid and error tolerant applications

In the modern applications there are lot of computing resources starting from Central Processing Units, Networks on Chips to Field Programmable Gate Arrays, each catering various types of operations. These factors motivate this research, to exploit 16-bit High Performance Variable Accuracy Reconfigurable Adder (HPVARA) and High Performance Error Tolerant Adder (HPETA-III) which are used extensively in many computing architectures for hybrid and error tolerant applications. The simulation based research outcome of the proposed HPVARA structure shows 13.69%, 15.95%, 9.82%, 22.53%, 13.56% improved Area Delay Product and 12.15%, 11.86%, 8.74%, 15.12%, 14.96% improved Power Delay Product with the computational outputs varying between 91.788% and 100% with the input operand pair compared to the existing ACA-I, ACA-II, GDA, VARA4 and conventional CSLA architectures. The second part of the research is focused on optimizing the design of the High Performance Error Tolerant Adder (HPETA-III). The proposed HPETA-III design performance is evaluated to offer a savings of logic gate count ranges from 268, 212, 173, 184, 196, 172, 68, 76, 60, 21 with respect to CSLA, VARA4, HSSSA, SAET-CSLA, ETCSLA, HSETA, HPETA-I, HPETA-II, CEETA, CEETA1 architectures respectively and also interesting results have been observed with reduced power, delay, PDP and ADP.