Analysis of Kogge-Stone and ladner fischer parallel prefix adder using verilog HDL

On this paper there is a study of different type of parallel prefix adders. As we know that adders are the basic building block of any Digital Circuits. Now a Days high speed circuits are used for various applications like communication circuits, hardware for Machine learning algorithms, Image processing algorithms etc. Various types of parallel prefix adders are used for different application. For Doing the Study of parallel Prefix adders we use Verilog HDL for the function description and then mapped the functionality on FPGA technology library using ISE14.5. The experimental results based on the design and constraints explains that the performance of Ladner fischner adder is better than Kogge-Stone.