Performance Evaluation of FinFET Device Under Nanometer Regime for Ultra-low Power Applications

For Ultra Large-Scale Integration (ULSI), the most promising device is multi gate Fin Field Effect Transistor (FinFET), as it offers reduced leakage current and better short channel performance. Modern design methodologies for 5 nm node NMOS FinFET transistors are examined in this paper to realize low power and low off state current (I off ) needs. Changing the punch through stop implant dose, source and drain junction placement, gate work function, Drain Induced Barrier Lowering (DIBL), and sub-threshold slope in combination with cut-in voltage yields the Ioff and Ion (on state current). Source drain expansion design, Fin doping concentration, and gate work function selection are exploited such that a FinFET device provides the requirements of low power and ultra-low power transistors.