Novel low-power pipelined DCT processor for real-time IoT applications

This research proposes a novel scalable Discrete Cosine transform (DCT) processor. It is based on a shared-resource enhanced Coordinate Rotation Digital Computer (CORDIC) unit, in a modified Loeffler architecture. All micro-rotation operations have moved to the last stages, and are implemented as one unified block in an overlapped form to reduce the utilization area. Also, the beginning stages consist of multiple-delay feedback butterfly units. The hardware-efficient pipelining method of the processor is another reason to reduce the power consumption. This is important while the purpose is resource-constraint IoT devices whereas establishing strong edge servers is not feasible everywhere. Especially in the case of modern video compression standards which demand higher points for DCT such as high efficiency video coding (HEVC) low-power design is crucial. Ubiquitous computing, Big Data and Cloud Services, IoT-Enabled Web are computation-intensive applications. Thus, power reduction of wireless networks of sensors such as, Bluetooth, RFID Wi-Fi, and smartphones, tablets, camcorders are in great demand. In-order input, and output is the proposed design’s advantage. Furthermore, due to utilization of shared-resource CORDIC-II unit, and reduction of adding, shifting operations, in size, and number, the architecture has high performance in short word lengths (WL) in comparison to state-of-the-art DCT processors.