Machine Allocation in Semiconductor Wafer Fabrication Systems: A Simulation-Based Approach

The problem of maximizing the throughput of Semiconductor Wafer Fabrication Systems is addressed. We model the fabrication systems as a Stochastic Timed Automata and design a discrete-event simulation scheme. The simulation scheme is explicit, fast and achieves high fidelity which captures the feature of reentrant process flow and is flexible to accommodate diversified wafer lot scheduling policies. A series of Marginal Machine Allocation Algorithms are proposed to sequentially allocate machines. Numerical experiments suggest the designed methods are efficient to find good allocation solutions.