A yield-enhanced global optimization methodology for analog circuit based on extreme value theory

The challenge in variation-aware circuit optimization with consideration of yield is the trade-off between optimized performance, yield and optimization runtime. This paper presents a practical variation- aware circuit global optimization framework named COYE, which shows the advantages on performance, yield and runtime. It uses an approach called constraint violation elimination （CVE） in global search phase to prune initial starting points and uses the gradient-based method in local search to locate optimum. The worst-case analysis （WCA）, which is necessary for variation-aware circuit optimization, is nested in the local optimization process. The efficiency is significantly improved by a novel method based on extreme value theory （EVT）. Our EVT-based method is also the first one that allows users to control the target yield such that under-design or over-design can be avoided. A design example in TSMC 65 nm technology is illustrated in the paper where all performance achieves three-sigma yield with consideration of environmental and inter-die/intra-die process variations.