Efficient implementation of a DSIG-JLT-based multiplexer and demultiplexer using different logic styles at 20-nm technology

The aim of this paper is to propose a compact device to design a multiplexer and demultiplexer which can reduce the circuit area while maintaining competitive performance. A novel device, the dielectric-separated independent-gate junctionless transistor (DSIG-JLT), is used to implement functional lo...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Veröffentlicht in:Journal of computational electronics 2023-12, Vol.22 (6), p.1626-1635
Hauptverfasser: Garg, Neha, Pratap, Yogesh, Kabra, Sneha
Format: Artikel
Sprache:eng
Schlagworte:
Online-Zugang:Volltext
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:The aim of this paper is to propose a compact device to design a multiplexer and demultiplexer which can reduce the circuit area while maintaining competitive performance. A novel device, the dielectric-separated independent-gate junctionless transistor (DSIG-JLT), is used to implement functional logic of a multiplexer and demultiplexer. The DSIG-JLT has four gates that can be electrically controlled in multiple ways to realize different digital logics. The DSIG-JLT is used to realize a 2 × 1 multiplexer and 1 × 2 demultiplexer by two different logic styles. The 2 × 1 multiplexer is implemented using four transistors, and the 1 × 2 demultiplexer is implemented using five transistors by NAND logic (logic style-1). Further, by using mixed logic, the 2 × 1 multiplexer is designed using three transistors, and the 1 × 2 demultiplexer using four transistors (logic style-2). A 4 × 1 multiplexer is also implemented using eight transistors. The propagation delay, rise time, and fall time of the 2 × 1 multiplexer (logic style-1) are calculated and are found to be 24.45 ps, 31 ps, and 8.2 ps, respectively, at a supply voltage ( V DD ) of 1 V. It is found that with a change in supply voltage from 0.7 to 1.0 V, the delay, rise time, and fall time decrease by 17.2%, 11.4%, and 65.69%, respectively. Simulations are carried using the ATLAS 3D device simulator in mixed mode. Graphical abstract
ISSN:1569-8025
1572-8137
DOI:10.1007/s10825-023-02099-5