Designing high-performance thermally stable repeaters for nano-interconnects

To enhance their performance, various designs of carbon nanotube (CNT) interconnects were analyzed and compared with conventional copper interconnects. To ameliorate the propagation delay of very long interconnect lines, smart buffers are inserted as repeaters along the lines. The existing buffer designs discussed here, including the conventional, LECTOR, Schmitt, and current-mode logic (CML) types, were implemented using both CNT and metal–oxide–semiconductor (MOS) technology for comparison in different combinations, viz. MOS repeater–Cu interconnect and CNT repeater–CNT interconnect. Furthermore, the proposed buffer designs use power gating techniques and an automated toggling approach to reduce the delay, besides mitigating the average power consumption. Compared with the aforementioned existing buffers, the proposed design 1 offers a 98 % saving in the dynamic power with a 64 % reduction in the propagation delay, but at the cost of higher leakage power consumption. The proposed design 2 offers a 99.86 % saving in the dynamic power with an 88 % reduction in the leakage power, reducing the delay by 52 %. The proposed design 3 results in a 99.94 % saving in the dynamic power and 93 % in the leakage power, but with a delay penalty. The results of the analysis of their electrothermal performance at temperatures ranging from 200 to 450 K revealed that the increases in the delay and power with rise in temperature were relatively greater for the MOS repeater–Cu interconnect combination compared with the CNT repeater–CNT interconnect combination. Simulations at the 32-nm technology node were carried out using HSPICE by considering a section of a long interconnect line as a driver interconnect load (DIL) system, using the Stanford SPICE model for CNT and the Berkeley Short-Channel IGFET Model (BSIM)4 Predictive Technology Model (PTM) for MOS.