Novel design for a memristor-based full adder using a new IMPLY logic approach

This paper presents and evaluates a novel approach based on material implementation to improve the performance of a 1-bit memristor-based full adder. In addition, two new efficient architectures are presented and evaluated for an 8-bit memristor-based full adder, serial memristor-based full adder and parallel-serial memristor-based full adder. Using the proposed approach, the number of required steps to accumulate the sum and carry-out in the proposed serial and parallel-serial 8-bit memristor-based full adder architectures is 168 and 56, respectively. Moreover, the number of required memristors in the proposed serial and parallel-serial memristor-based full adder architectures is 19 and 33, respectively. The evaluation results show that both delay and density are improved in the proposed architectures compared to other memristor-based full adder architectures.