New design for error-resilient approximate multipliers used in image processing in CNTFET technology

Approximate computing is a new approach to reducing power consumption and complexity, increasing performance, and can generate a trade-off between accuracy and power-delay-area efficiency in error-resilient applications. As multiplication is applied in multimedia processing, and it is time-consuming, implementing efficient circuits for multipliers is essential. This article presents novel recursive approximate multipliers and new approximate multipliers based on partial products grouping (clustering). These proposed approximate multipliers are applied in the structure of error-resilient image processing applications: image multiplication, image sharpening, and smoothing. Application-level simulation results show that the proposed multipliers improve the accuracy of their counterparts, while the circuit-level simulation results demonstrate acceptable delay and power consumption. Three Figures Of Merit (FOMs) were introduced to compromise between circuit evaluation criteria and error analysis metrics. By examining these FOMs, the proposed circuits have created a suitable trade-off between circuit and error evaluation criteria compared to other circuits.