Time-dependent dielectric breakdown of SiC-CMOS technology for harsh environments

To estimate the failure time of silicon carbide (SiC) integrated circuits in harsh environments, the activation energy (Ea) and field acceleration factor of SiC n-channel MOS (nMOS) and p-channel MOS (pMOS) were measured using time-dependent dielectric breakdown testing at constant voltage stress in...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Veröffentlicht in:Applied physics letters 2024-01, Vol.124 (4)
Hauptverfasser: Masunaga, Masahiro, Sasago, Yoshitaka, Mori, Yuki, Hisamoto, Digh
Format: Artikel
Sprache:eng
Schlagworte:
Online-Zugang:Volltext
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue 4
container_start_page
container_title Applied physics letters
container_volume 124
creator Masunaga, Masahiro
Sasago, Yoshitaka
Mori, Yuki
Hisamoto, Digh
description To estimate the failure time of silicon carbide (SiC) integrated circuits in harsh environments, the activation energy (Ea) and field acceleration factor of SiC n-channel MOS (nMOS) and p-channel MOS (pMOS) were measured using time-dependent dielectric breakdown testing at constant voltage stress in the range of 25–350 °C. Ea around 300 °C was 0.7 eV for nMOS and 0.66 eV for pMOS, which was about twice as high as that below 150 °C and did not differ greatly depending on the conductivity type. The gate dielectric breakdown mechanism shifted from the 1/E model to the E model as the temperature rose, and this is thought to have caused the Ea to change. The field acceleration factor in the E model at 300 °C was 2.7 and 2.3 cm/MV for nMOS and pMOS, respectively. The maximum operating electric fields of nMOS and pMOS for a 100-year lifetime are 6.8 and −7.2 MV/cm, which are over 25% lower than the fields at room temperature, mainly due to a shift in the dominant breakdown model. A more conservative failure time design will be required for SiC-ICs exposed to high temperatures.
doi_str_mv 10.1063/5.0184689
format Article
fullrecord <record><control><sourceid>proquest_scita</sourceid><recordid>TN_cdi_proquest_journals_2917370539</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>2917370539</sourcerecordid><originalsourceid>FETCH-LOGICAL-c327t-87e3340c8309b363b43694a894acc6a1179440780f1f202b469f78cea075a3e03</originalsourceid><addsrcrecordid>eNp90E1LAzEQBuAgCtbqwX8Q8KSwdbKzu0mOsvgFSpHW85LNJja1TWqyVfrvXWnPHoZh4OEdeAm5ZDBhUOFtOQEmikrIIzJiwHmGjIljMgIAzCpZslNyltJyOMsccUTe5m5tss5sjO-M72nnzMroPjpN22jUZxd-PA2Wzlyd1a_TGe2NXviwCh87akOkCxXTghr_7WLw6yEhnZMTq1bJXBz2mLw_3M_rp-xl-vhc371kGnPeZ4IbxAK0QJAtVtgWWMlCiWG0rhRjXBYFcAGW2Rzytqik5UIbBbxUaADH5Gqfu4nha2tS3yzDNvrhZZNLxpFDiXJQ13ulY0gpGttsoluruGsYNH-NNWVzaGywN3ubtOtV74L_B_8C6wVpSQ</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>2917370539</pqid></control><display><type>article</type><title>Time-dependent dielectric breakdown of SiC-CMOS technology for harsh environments</title><source>AIP Journals Complete</source><source>Alma/SFX Local Collection</source><creator>Masunaga, Masahiro ; Sasago, Yoshitaka ; Mori, Yuki ; Hisamoto, Digh</creator><creatorcontrib>Masunaga, Masahiro ; Sasago, Yoshitaka ; Mori, Yuki ; Hisamoto, Digh</creatorcontrib><description>To estimate the failure time of silicon carbide (SiC) integrated circuits in harsh environments, the activation energy (Ea) and field acceleration factor of SiC n-channel MOS (nMOS) and p-channel MOS (pMOS) were measured using time-dependent dielectric breakdown testing at constant voltage stress in the range of 25–350 °C. Ea around 300 °C was 0.7 eV for nMOS and 0.66 eV for pMOS, which was about twice as high as that below 150 °C and did not differ greatly depending on the conductivity type. The gate dielectric breakdown mechanism shifted from the 1/E model to the E model as the temperature rose, and this is thought to have caused the Ea to change. The field acceleration factor in the E model at 300 °C was 2.7 and 2.3 cm/MV for nMOS and pMOS, respectively. The maximum operating electric fields of nMOS and pMOS for a 100-year lifetime are 6.8 and −7.2 MV/cm, which are over 25% lower than the fields at room temperature, mainly due to a shift in the dominant breakdown model. A more conservative failure time design will be required for SiC-ICs exposed to high temperatures.</description><identifier>ISSN: 0003-6951</identifier><identifier>EISSN: 1077-3118</identifier><identifier>DOI: 10.1063/5.0184689</identifier><identifier>CODEN: APPLAB</identifier><language>eng</language><publisher>Melville: American Institute of Physics</publisher><subject>Dielectric breakdown ; Electric fields ; Failure times ; High temperature ; Integrated circuits ; Metal oxide semiconductors ; Room temperature ; Silicon carbide ; Time dependence ; Time measurement</subject><ispartof>Applied physics letters, 2024-01, Vol.124 (4)</ispartof><rights>Author(s)</rights><rights>2024 Author(s). Published under an exclusive license by AIP Publishing.</rights><lds50>peer_reviewed</lds50><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c327t-87e3340c8309b363b43694a894acc6a1179440780f1f202b469f78cea075a3e03</citedby><cites>FETCH-LOGICAL-c327t-87e3340c8309b363b43694a894acc6a1179440780f1f202b469f78cea075a3e03</cites><orcidid>0000-0002-8657-6515 ; 0000-0003-1464-8193 ; 0009-0006-5265-3750 ; 0009-0005-7717-5049</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://pubs.aip.org/apl/article-lookup/doi/10.1063/5.0184689$$EHTML$$P50$$Gscitation$$H</linktohtml><link.rule.ids>314,776,780,790,4498,27901,27902,76127</link.rule.ids></links><search><creatorcontrib>Masunaga, Masahiro</creatorcontrib><creatorcontrib>Sasago, Yoshitaka</creatorcontrib><creatorcontrib>Mori, Yuki</creatorcontrib><creatorcontrib>Hisamoto, Digh</creatorcontrib><title>Time-dependent dielectric breakdown of SiC-CMOS technology for harsh environments</title><title>Applied physics letters</title><description>To estimate the failure time of silicon carbide (SiC) integrated circuits in harsh environments, the activation energy (Ea) and field acceleration factor of SiC n-channel MOS (nMOS) and p-channel MOS (pMOS) were measured using time-dependent dielectric breakdown testing at constant voltage stress in the range of 25–350 °C. Ea around 300 °C was 0.7 eV for nMOS and 0.66 eV for pMOS, which was about twice as high as that below 150 °C and did not differ greatly depending on the conductivity type. The gate dielectric breakdown mechanism shifted from the 1/E model to the E model as the temperature rose, and this is thought to have caused the Ea to change. The field acceleration factor in the E model at 300 °C was 2.7 and 2.3 cm/MV for nMOS and pMOS, respectively. The maximum operating electric fields of nMOS and pMOS for a 100-year lifetime are 6.8 and −7.2 MV/cm, which are over 25% lower than the fields at room temperature, mainly due to a shift in the dominant breakdown model. A more conservative failure time design will be required for SiC-ICs exposed to high temperatures.</description><subject>Dielectric breakdown</subject><subject>Electric fields</subject><subject>Failure times</subject><subject>High temperature</subject><subject>Integrated circuits</subject><subject>Metal oxide semiconductors</subject><subject>Room temperature</subject><subject>Silicon carbide</subject><subject>Time dependence</subject><subject>Time measurement</subject><issn>0003-6951</issn><issn>1077-3118</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2024</creationdate><recordtype>article</recordtype><recordid>eNp90E1LAzEQBuAgCtbqwX8Q8KSwdbKzu0mOsvgFSpHW85LNJja1TWqyVfrvXWnPHoZh4OEdeAm5ZDBhUOFtOQEmikrIIzJiwHmGjIljMgIAzCpZslNyltJyOMsccUTe5m5tss5sjO-M72nnzMroPjpN22jUZxd-PA2Wzlyd1a_TGe2NXviwCh87akOkCxXTghr_7WLw6yEhnZMTq1bJXBz2mLw_3M_rp-xl-vhc371kGnPeZ4IbxAK0QJAtVtgWWMlCiWG0rhRjXBYFcAGW2Rzytqik5UIbBbxUaADH5Gqfu4nha2tS3yzDNvrhZZNLxpFDiXJQ13ulY0gpGttsoluruGsYNH-NNWVzaGywN3ubtOtV74L_B_8C6wVpSQ</recordid><startdate>20240122</startdate><enddate>20240122</enddate><creator>Masunaga, Masahiro</creator><creator>Sasago, Yoshitaka</creator><creator>Mori, Yuki</creator><creator>Hisamoto, Digh</creator><general>American Institute of Physics</general><scope>AAYXX</scope><scope>CITATION</scope><scope>8FD</scope><scope>H8D</scope><scope>L7M</scope><orcidid>https://orcid.org/0000-0002-8657-6515</orcidid><orcidid>https://orcid.org/0000-0003-1464-8193</orcidid><orcidid>https://orcid.org/0009-0006-5265-3750</orcidid><orcidid>https://orcid.org/0009-0005-7717-5049</orcidid></search><sort><creationdate>20240122</creationdate><title>Time-dependent dielectric breakdown of SiC-CMOS technology for harsh environments</title><author>Masunaga, Masahiro ; Sasago, Yoshitaka ; Mori, Yuki ; Hisamoto, Digh</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c327t-87e3340c8309b363b43694a894acc6a1179440780f1f202b469f78cea075a3e03</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2024</creationdate><topic>Dielectric breakdown</topic><topic>Electric fields</topic><topic>Failure times</topic><topic>High temperature</topic><topic>Integrated circuits</topic><topic>Metal oxide semiconductors</topic><topic>Room temperature</topic><topic>Silicon carbide</topic><topic>Time dependence</topic><topic>Time measurement</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Masunaga, Masahiro</creatorcontrib><creatorcontrib>Sasago, Yoshitaka</creatorcontrib><creatorcontrib>Mori, Yuki</creatorcontrib><creatorcontrib>Hisamoto, Digh</creatorcontrib><collection>CrossRef</collection><collection>Technology Research Database</collection><collection>Aerospace Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>Applied physics letters</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Masunaga, Masahiro</au><au>Sasago, Yoshitaka</au><au>Mori, Yuki</au><au>Hisamoto, Digh</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Time-dependent dielectric breakdown of SiC-CMOS technology for harsh environments</atitle><jtitle>Applied physics letters</jtitle><date>2024-01-22</date><risdate>2024</risdate><volume>124</volume><issue>4</issue><issn>0003-6951</issn><eissn>1077-3118</eissn><coden>APPLAB</coden><abstract>To estimate the failure time of silicon carbide (SiC) integrated circuits in harsh environments, the activation energy (Ea) and field acceleration factor of SiC n-channel MOS (nMOS) and p-channel MOS (pMOS) were measured using time-dependent dielectric breakdown testing at constant voltage stress in the range of 25–350 °C. Ea around 300 °C was 0.7 eV for nMOS and 0.66 eV for pMOS, which was about twice as high as that below 150 °C and did not differ greatly depending on the conductivity type. The gate dielectric breakdown mechanism shifted from the 1/E model to the E model as the temperature rose, and this is thought to have caused the Ea to change. The field acceleration factor in the E model at 300 °C was 2.7 and 2.3 cm/MV for nMOS and pMOS, respectively. The maximum operating electric fields of nMOS and pMOS for a 100-year lifetime are 6.8 and −7.2 MV/cm, which are over 25% lower than the fields at room temperature, mainly due to a shift in the dominant breakdown model. A more conservative failure time design will be required for SiC-ICs exposed to high temperatures.</abstract><cop>Melville</cop><pub>American Institute of Physics</pub><doi>10.1063/5.0184689</doi><tpages>4</tpages><orcidid>https://orcid.org/0000-0002-8657-6515</orcidid><orcidid>https://orcid.org/0000-0003-1464-8193</orcidid><orcidid>https://orcid.org/0009-0006-5265-3750</orcidid><orcidid>https://orcid.org/0009-0005-7717-5049</orcidid><oa>free_for_read</oa></addata></record>
fulltext fulltext
identifier ISSN: 0003-6951
ispartof Applied physics letters, 2024-01, Vol.124 (4)
issn 0003-6951
1077-3118
language eng
recordid cdi_proquest_journals_2917370539
source AIP Journals Complete; Alma/SFX Local Collection
subjects Dielectric breakdown
Electric fields
Failure times
High temperature
Integrated circuits
Metal oxide semiconductors
Room temperature
Silicon carbide
Time dependence
Time measurement
title Time-dependent dielectric breakdown of SiC-CMOS technology for harsh environments
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-03T21%3A43%3A22IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_scita&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Time-dependent%20dielectric%20breakdown%20of%20SiC-CMOS%20technology%20for%20harsh%20environments&rft.jtitle=Applied%20physics%20letters&rft.au=Masunaga,%20Masahiro&rft.date=2024-01-22&rft.volume=124&rft.issue=4&rft.issn=0003-6951&rft.eissn=1077-3118&rft.coden=APPLAB&rft_id=info:doi/10.1063/5.0184689&rft_dat=%3Cproquest_scita%3E2917370539%3C/proquest_scita%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=2917370539&rft_id=info:pmid/&rfr_iscdi=true