Time-dependent dielectric breakdown of SiC-CMOS technology for harsh environments
To estimate the failure time of silicon carbide (SiC) integrated circuits in harsh environments, the activation energy (Ea) and field acceleration factor of SiC n-channel MOS (nMOS) and p-channel MOS (pMOS) were measured using time-dependent dielectric breakdown testing at constant voltage stress in...
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description | To estimate the failure time of silicon carbide (SiC) integrated circuits in harsh environments, the activation energy (Ea) and field acceleration factor of SiC n-channel MOS (nMOS) and p-channel MOS (pMOS) were measured using time-dependent dielectric breakdown testing at constant voltage stress in the range of 25–350 °C. Ea around 300 °C was 0.7 eV for nMOS and 0.66 eV for pMOS, which was about twice as high as that below 150 °C and did not differ greatly depending on the conductivity type. The gate dielectric breakdown mechanism shifted from the 1/E model to the E model as the temperature rose, and this is thought to have caused the Ea to change. The field acceleration factor in the E model at 300 °C was 2.7 and 2.3 cm/MV for nMOS and pMOS, respectively. The maximum operating electric fields of nMOS and pMOS for a 100-year lifetime are 6.8 and −7.2 MV/cm, which are over 25% lower than the fields at room temperature, mainly due to a shift in the dominant breakdown model. A more conservative failure time design will be required for SiC-ICs exposed to high temperatures. |
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Ea around 300 °C was 0.7 eV for nMOS and 0.66 eV for pMOS, which was about twice as high as that below 150 °C and did not differ greatly depending on the conductivity type. The gate dielectric breakdown mechanism shifted from the 1/E model to the E model as the temperature rose, and this is thought to have caused the Ea to change. The field acceleration factor in the E model at 300 °C was 2.7 and 2.3 cm/MV for nMOS and pMOS, respectively. The maximum operating electric fields of nMOS and pMOS for a 100-year lifetime are 6.8 and −7.2 MV/cm, which are over 25% lower than the fields at room temperature, mainly due to a shift in the dominant breakdown model. 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Ea around 300 °C was 0.7 eV for nMOS and 0.66 eV for pMOS, which was about twice as high as that below 150 °C and did not differ greatly depending on the conductivity type. The gate dielectric breakdown mechanism shifted from the 1/E model to the E model as the temperature rose, and this is thought to have caused the Ea to change. The field acceleration factor in the E model at 300 °C was 2.7 and 2.3 cm/MV for nMOS and pMOS, respectively. The maximum operating electric fields of nMOS and pMOS for a 100-year lifetime are 6.8 and −7.2 MV/cm, which are over 25% lower than the fields at room temperature, mainly due to a shift in the dominant breakdown model. A more conservative failure time design will be required for SiC-ICs exposed to high temperatures.</description><subject>Dielectric breakdown</subject><subject>Electric fields</subject><subject>Failure times</subject><subject>High temperature</subject><subject>Integrated circuits</subject><subject>Metal oxide semiconductors</subject><subject>Room temperature</subject><subject>Silicon carbide</subject><subject>Time dependence</subject><subject>Time measurement</subject><issn>0003-6951</issn><issn>1077-3118</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2024</creationdate><recordtype>article</recordtype><recordid>eNp90E1LAzEQBuAgCtbqwX8Q8KSwdbKzu0mOsvgFSpHW85LNJja1TWqyVfrvXWnPHoZh4OEdeAm5ZDBhUOFtOQEmikrIIzJiwHmGjIljMgIAzCpZslNyltJyOMsccUTe5m5tss5sjO-M72nnzMroPjpN22jUZxd-PA2Wzlyd1a_TGe2NXviwCh87akOkCxXTghr_7WLw6yEhnZMTq1bJXBz2mLw_3M_rp-xl-vhc371kGnPeZ4IbxAK0QJAtVtgWWMlCiWG0rhRjXBYFcAGW2Rzytqik5UIbBbxUaADH5Gqfu4nha2tS3yzDNvrhZZNLxpFDiXJQ13ulY0gpGttsoluruGsYNH-NNWVzaGywN3ubtOtV74L_B_8C6wVpSQ</recordid><startdate>20240122</startdate><enddate>20240122</enddate><creator>Masunaga, Masahiro</creator><creator>Sasago, Yoshitaka</creator><creator>Mori, Yuki</creator><creator>Hisamoto, Digh</creator><general>American Institute of Physics</general><scope>AAYXX</scope><scope>CITATION</scope><scope>8FD</scope><scope>H8D</scope><scope>L7M</scope><orcidid>https://orcid.org/0000-0002-8657-6515</orcidid><orcidid>https://orcid.org/0000-0003-1464-8193</orcidid><orcidid>https://orcid.org/0009-0006-5265-3750</orcidid><orcidid>https://orcid.org/0009-0005-7717-5049</orcidid></search><sort><creationdate>20240122</creationdate><title>Time-dependent dielectric breakdown of SiC-CMOS technology for harsh environments</title><author>Masunaga, Masahiro ; Sasago, Yoshitaka ; Mori, Yuki ; Hisamoto, Digh</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c327t-87e3340c8309b363b43694a894acc6a1179440780f1f202b469f78cea075a3e03</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2024</creationdate><topic>Dielectric breakdown</topic><topic>Electric fields</topic><topic>Failure times</topic><topic>High temperature</topic><topic>Integrated circuits</topic><topic>Metal oxide semiconductors</topic><topic>Room temperature</topic><topic>Silicon carbide</topic><topic>Time dependence</topic><topic>Time measurement</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Masunaga, Masahiro</creatorcontrib><creatorcontrib>Sasago, Yoshitaka</creatorcontrib><creatorcontrib>Mori, Yuki</creatorcontrib><creatorcontrib>Hisamoto, Digh</creatorcontrib><collection>CrossRef</collection><collection>Technology Research Database</collection><collection>Aerospace Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>Applied physics letters</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Masunaga, Masahiro</au><au>Sasago, Yoshitaka</au><au>Mori, Yuki</au><au>Hisamoto, Digh</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Time-dependent dielectric breakdown of SiC-CMOS technology for harsh environments</atitle><jtitle>Applied physics letters</jtitle><date>2024-01-22</date><risdate>2024</risdate><volume>124</volume><issue>4</issue><issn>0003-6951</issn><eissn>1077-3118</eissn><coden>APPLAB</coden><abstract>To estimate the failure time of silicon carbide (SiC) integrated circuits in harsh environments, the activation energy (Ea) and field acceleration factor of SiC n-channel MOS (nMOS) and p-channel MOS (pMOS) were measured using time-dependent dielectric breakdown testing at constant voltage stress in the range of 25–350 °C. Ea around 300 °C was 0.7 eV for nMOS and 0.66 eV for pMOS, which was about twice as high as that below 150 °C and did not differ greatly depending on the conductivity type. The gate dielectric breakdown mechanism shifted from the 1/E model to the E model as the temperature rose, and this is thought to have caused the Ea to change. The field acceleration factor in the E model at 300 °C was 2.7 and 2.3 cm/MV for nMOS and pMOS, respectively. The maximum operating electric fields of nMOS and pMOS for a 100-year lifetime are 6.8 and −7.2 MV/cm, which are over 25% lower than the fields at room temperature, mainly due to a shift in the dominant breakdown model. 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subjects | Dielectric breakdown Electric fields Failure times High temperature Integrated circuits Metal oxide semiconductors Room temperature Silicon carbide Time dependence Time measurement |
title | Time-dependent dielectric breakdown of SiC-CMOS technology for harsh environments |
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