Time-dependent dielectric breakdown of SiC-CMOS technology for harsh environments
To estimate the failure time of silicon carbide (SiC) integrated circuits in harsh environments, the activation energy (Ea) and field acceleration factor of SiC n-channel MOS (nMOS) and p-channel MOS (pMOS) were measured using time-dependent dielectric breakdown testing at constant voltage stress in...
Gespeichert in:
Veröffentlicht in: | Applied physics letters 2024-01, Vol.124 (4) |
---|---|
Hauptverfasser: | , , , |
Format: | Artikel |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
Zusammenfassung: | To estimate the failure time of silicon carbide (SiC) integrated circuits in harsh environments, the activation energy (Ea) and field acceleration factor of SiC n-channel MOS (nMOS) and p-channel MOS (pMOS) were measured using time-dependent dielectric breakdown testing at constant voltage stress in the range of 25–350 °C. Ea around 300 °C was 0.7 eV for nMOS and 0.66 eV for pMOS, which was about twice as high as that below 150 °C and did not differ greatly depending on the conductivity type. The gate dielectric breakdown mechanism shifted from the 1/E model to the E model as the temperature rose, and this is thought to have caused the Ea to change. The field acceleration factor in the E model at 300 °C was 2.7 and 2.3 cm/MV for nMOS and pMOS, respectively. The maximum operating electric fields of nMOS and pMOS for a 100-year lifetime are 6.8 and −7.2 MV/cm, which are over 25% lower than the fields at room temperature, mainly due to a shift in the dominant breakdown model. A more conservative failure time design will be required for SiC-ICs exposed to high temperatures. |
---|---|
ISSN: | 0003-6951 1077-3118 |
DOI: | 10.1063/5.0184689 |