Comparative analysis of C-element and D-element double edge triggered flip flop for power efficient VLSI applications

In this paper the work has been carried out for attaining a very impressive achievement of low power digital circuits, without compromising in dual edge triggering phenomenon. In this work different strategies of static dual-edge triggered flip-flops (DET) which show exclusive circuit behaviour due to the usage of C-elements and D-element has been analysed. In D-element again, the two different categories like static and dynamic D-element were analysed in 130nm technology. One of the key elements used in asynchronous control circuits is the C-element. The performance metrics were analysed and tabulated their characteristics, through mentor graphics in 130nm technology.