A wide input voltage range, high power supply rejection low‐dropout regulator with a closed‐loop charge pump for sensor front‐end circuits
Summary This paper presents a low dropout regulator (LDO) with a wide input voltage range and high power supply rejection (PSR) for Hall sensor front‐end circuits, which is fabricated with a 0.18 μm BCD process. A topology in which a closed‐loop charge pump biases the gate of two‐stage cascode NMOS...
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Veröffentlicht in: | International journal of circuit theory and applications 2024-01, Vol.52 (1), p.27-43 |
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Format: | Artikel |
Sprache: | eng |
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This paper presents a low dropout regulator (LDO) with a wide input voltage range and high power supply rejection (PSR) for Hall sensor front‐end circuits, which is fabricated with a 0.18 μm BCD process. A topology in which a closed‐loop charge pump biases the gate of two‐stage cascode NMOS pass transistors is proposed to increase immunity to electromagnetic interference (EMI) capability for automotive applications. Furthermore, a power‐down protection circuit is proposed to maintain the reliability of the system, and a novel implementation of the charge pump unit is presented to improve the influence of the body effect. Detailed derivation regarding the analyses of the simplified small‐signal model of the closed‐loop charge pump, the loop stability, and the PSR at various frequency bands is given. Simulation and measurement results show that the proposed LDO can operate with the input voltage from 5 to 40 V, providing up to 60 mA current drive capability, and its minimum operating voltage is 2.5 V with a 10 mA load capacity. Moreover, results verify that measured PSR is better than −45 dB at 1.5 kHz, and measured PSR is better than −30 dB at 15 MHz. The results confirm that the obtained parameters of line and load regulations are significantly improved to 1.86 mV/V and 1.75 mV/mA, respectively.
This paper presents a low dropout regulator (LDO) with a wide input voltage range and high power supply rejection (PSR) for Hall sensor front‐end circuits. And a topology in which a closed‐loop charge pump biases the gate of two‐stage cascode NMOS pass transistors is proposed. |
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ISSN: | 0098-9886 1097-007X |
DOI: | 10.1002/cta.3766 |