Design & Implementation of Multi Stage Multi-Rate Filter for Digital Receivers

The focus of this research is to present a decimation filter architecture for wireless receivers that employs the fewest possible logics and allows the reception of signals from a variety of communication protocols. It also entails the design process of twin and multi-stage multi-rate filter designs with low VLSI cost functions. The first component of the first architecture's twin stage decimation filter network is Higher Order Filter (HDF). Following the Higher Order Filter stage, a typical Corrector/Compensating Finite Impulse Response (FIR) circuit is used to remove aliasing components of the HDF and produce a smooth pass band response. The Multi Standard Decimation Filter (MSDF) structure is offered as the second multi-stage design to address the necessity for receipt of multi-standard receiver signals. The MSDF architecture is created for two wireless communication standards in this research: GSM and WiMAX. According on the performance measurements, the suggested multi stage MSDF filter structure saves 75 percent of the space and reduces dynamic power dissipation by 81.15 percent. When compared to the two stage filter, the suggested MSDF has a speed gain of 33.86 percent. Thus, the suggested MSDF architecture implementation uses a multistage decimation strategy to provide area reduction and low power solutions, and it is better adapted for multi-standard communication digital receivers.