Parallel Doubly Fed Symbol Timing Recovery Algorithm and FPGA Implementation for Burst Broadband Satellite Access

Existing symbol timing recovery (STR) cannot simultaneously meet the performance requirements of broadband satellite internet for throughput, convergence speed, convergence accuracy, and implementation complexity. Focusing on burst single-carrier communications widely used in broadband satellite systems, we proposed a parallel doubly fed STR algorithm combining feedforward and feedback loop, in which the frequency-domain (FD) prefilter is also used to improve the algorithm's anti-self-noise capability. The corresponding field programmable gate array (FPGA) implementation with low complexity and highly parallel architecture is then accomplished. Simulation results show that the performance degradation caused by the proposed algorithm is less than 0.03 dB compared with the ideal performance when uncoded bit error rate (BER) equals 1e-4 and 64 quadrature amplitude modulation (QAM) modulation is considered. FPGA verification based on the XC7VX690T chip also shows that with 64 parallel inputs and 64-QAM modulation, the throughput rate of information bit can reach 19.2 Gb/s for our design with utilization of 17% look-up tables (LUTs) and 20% digital signal processing (DSP), respectively.