Extremely High-κ Hf0.2Zr0.8O2 Gate Stacks Integrated Into Eight Stacked Ge0.95Si0.05 Nanowires and Nanosheets nFETs to Boost ION
By taking advantage of extremely high dielectric constant ( \kappa ) of 47, the Hf0.2Zr0.8O2 gate stacks are integrated into the eight stacked high mobility Ge0.95Si0.05 channels with low thermal budget ( \leqq 450 °C) to significantly enhance the {I} _{ \mathrm{\scriptscriptstyle ON}} . Isotropic...
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description | By taking advantage of extremely high dielectric constant ( \kappa ) of 47, the Hf0.2Zr0.8O2 gate stacks are integrated into the eight stacked high mobility Ge0.95Si0.05 channels with low thermal budget ( \leqq 450 °C) to significantly enhance the {I} _{ \mathrm{\scriptscriptstyle ON}} . Isotropic wet etching by \text{H}_{{2}}\text{O}_{{2}} and HNO3 serve well during the channel release of nanowires and nanosheets, respectively. The simulated \kappa versus Zr concentration in HZO can show that the \kappa can have a peak value at Zr concentration around 80%. The eight stacked Ge0.95Si0.05 nanowires and nanosheets with Hf0.2Zr0.8O2 gate stacks achieve the record high {I} _{ \mathrm{\scriptscriptstyle ON}} per footprint of 9200~\mu \text{A} and record high {I} _{ \mathrm{\scriptscriptstyle ON}} per stack of 360~\mu \text{A} at {V} _{\text {OV}} ={V}_{\text {DS}} = 0.5 V, respectively, among all Si/GeSi/Ge 3-D nFETs. Moreover, the potential gate delay improvement by combining the extremely high- \kappa gate stacks and large floor number is studied by TCAD simulation using industrial device structures. |
doi_str_mv | 10.1109/TED.2023.3315685 |
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W.</creator><creatorcontrib>Chen, Wei-Jen ; Liu, Yi-Chun ; Chen, Yun-Wen ; Chen, Yu-Rui ; Lin, Hsin-Cheng ; Tu, Chien-Te ; Huang, Bo-Wei ; Liu, C. W.</creatorcontrib><description><![CDATA[By taking advantage of extremely high dielectric constant (<inline-formula> <tex-math notation="LaTeX">\kappa </tex-math></inline-formula>) of 47, the Hf0.2Zr0.8O2 gate stacks are integrated into the eight stacked high mobility Ge0.95Si0.05 channels with low thermal budget (<inline-formula> <tex-math notation="LaTeX">\leqq 450 </tex-math></inline-formula> °C) to significantly enhance the <inline-formula> <tex-math notation="LaTeX">{I} _{ \mathrm{\scriptscriptstyle ON}} </tex-math></inline-formula>. Isotropic wet etching by <inline-formula> <tex-math notation="LaTeX">\text{H}_{{2}}\text{O}_{{2}} </tex-math></inline-formula> and HNO3 serve well during the channel release of nanowires and nanosheets, respectively. The simulated <inline-formula> <tex-math notation="LaTeX">\kappa </tex-math></inline-formula> versus Zr concentration in HZO can show that the <inline-formula> <tex-math notation="LaTeX">\kappa </tex-math></inline-formula> can have a peak value at Zr concentration around 80%. The eight stacked Ge0.95Si0.05 nanowires and nanosheets with Hf0.2Zr0.8O2 gate stacks achieve the record high <inline-formula> <tex-math notation="LaTeX">{I} _{ \mathrm{\scriptscriptstyle ON}} </tex-math></inline-formula> per footprint of <inline-formula> <tex-math notation="LaTeX">9200~\mu \text{A} </tex-math></inline-formula> and record high <inline-formula> <tex-math notation="LaTeX">{I} _{ \mathrm{\scriptscriptstyle ON}} </tex-math></inline-formula> per stack of <inline-formula> <tex-math notation="LaTeX">360~\mu \text{A} </tex-math></inline-formula> at <inline-formula> <tex-math notation="LaTeX">{V} _{\text {OV}} ={V}_{\text {DS}} </tex-math></inline-formula> = 0.5 V, respectively, among all Si/GeSi/Ge 3-D nFETs. Moreover, the potential gate delay improvement by combining the extremely high-<inline-formula> <tex-math notation="LaTeX">\kappa </tex-math></inline-formula> gate stacks and large floor number is studied by TCAD simulation using industrial device structures.]]></description><identifier>ISSN: 0018-9383</identifier><identifier>EISSN: 1557-9646</identifier><identifier>DOI: 10.1109/TED.2023.3315685</identifier><identifier>CODEN: IETDAI</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Germanium ; Germanium silicon alloys ; GeSi ; high-k gate stacks ; highly stacked channels ; Logic gates ; Nanosheets ; Nanowires ; Silicon ; Stacks ; Wet etching ; Zirconium</subject><ispartof>IEEE transactions on electron devices, 2023-12, Vol.70 (12), p.6673-6679</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2023</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><orcidid>0000-0002-1405-8639 ; 0000-0002-6439-8754 ; 0000-0003-2832-1853 ; 0000-0002-1564-7750 ; 0000-0002-2110-4867 ; 0000-0002-3404-236X</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/10268397$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,776,780,792,27901,27902,54733</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/10268397$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Chen, Wei-Jen</creatorcontrib><creatorcontrib>Liu, Yi-Chun</creatorcontrib><creatorcontrib>Chen, Yun-Wen</creatorcontrib><creatorcontrib>Chen, Yu-Rui</creatorcontrib><creatorcontrib>Lin, Hsin-Cheng</creatorcontrib><creatorcontrib>Tu, Chien-Te</creatorcontrib><creatorcontrib>Huang, Bo-Wei</creatorcontrib><creatorcontrib>Liu, C. W.</creatorcontrib><title>Extremely High-κ Hf0.2Zr0.8O2 Gate Stacks Integrated Into Eight Stacked Ge0.95Si0.05 Nanowires and Nanosheets nFETs to Boost ION</title><title>IEEE transactions on electron devices</title><addtitle>TED</addtitle><description><![CDATA[By taking advantage of extremely high dielectric constant (<inline-formula> <tex-math notation="LaTeX">\kappa </tex-math></inline-formula>) of 47, the Hf0.2Zr0.8O2 gate stacks are integrated into the eight stacked high mobility Ge0.95Si0.05 channels with low thermal budget (<inline-formula> <tex-math notation="LaTeX">\leqq 450 </tex-math></inline-formula> °C) to significantly enhance the <inline-formula> <tex-math notation="LaTeX">{I} _{ \mathrm{\scriptscriptstyle ON}} </tex-math></inline-formula>. Isotropic wet etching by <inline-formula> <tex-math notation="LaTeX">\text{H}_{{2}}\text{O}_{{2}} </tex-math></inline-formula> and HNO3 serve well during the channel release of nanowires and nanosheets, respectively. The simulated <inline-formula> <tex-math notation="LaTeX">\kappa </tex-math></inline-formula> versus Zr concentration in HZO can show that the <inline-formula> <tex-math notation="LaTeX">\kappa </tex-math></inline-formula> can have a peak value at Zr concentration around 80%. The eight stacked Ge0.95Si0.05 nanowires and nanosheets with Hf0.2Zr0.8O2 gate stacks achieve the record high <inline-formula> <tex-math notation="LaTeX">{I} _{ \mathrm{\scriptscriptstyle ON}} </tex-math></inline-formula> per footprint of <inline-formula> <tex-math notation="LaTeX">9200~\mu \text{A} </tex-math></inline-formula> and record high <inline-formula> <tex-math notation="LaTeX">{I} _{ \mathrm{\scriptscriptstyle ON}} </tex-math></inline-formula> per stack of <inline-formula> <tex-math notation="LaTeX">360~\mu \text{A} </tex-math></inline-formula> at <inline-formula> <tex-math notation="LaTeX">{V} _{\text {OV}} ={V}_{\text {DS}} </tex-math></inline-formula> = 0.5 V, respectively, among all Si/GeSi/Ge 3-D nFETs. Moreover, the potential gate delay improvement by combining the extremely high-<inline-formula> <tex-math notation="LaTeX">\kappa </tex-math></inline-formula> gate stacks and large floor number is studied by TCAD simulation using industrial device structures.]]></description><subject>Germanium</subject><subject>Germanium silicon alloys</subject><subject>GeSi</subject><subject>high-k gate stacks</subject><subject>highly stacked channels</subject><subject>Logic gates</subject><subject>Nanosheets</subject><subject>Nanowires</subject><subject>Silicon</subject><subject>Stacks</subject><subject>Wet etching</subject><subject>Zirconium</subject><issn>0018-9383</issn><issn>1557-9646</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2023</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNotj89OAjEQxhujiYjePXho4nnX6f_2qLgCCYEDePGyKWwXFmEXtyXK0dfyIXwmq3ia-X7zfTMZhK4JpISAuZtljykFylLGiJBanKAOEUIlRnJ5ijoARCeGaXaOLrxfRyk5px30mX2E1m3d5oAH1XKVfH_hQQkpfWkh1ROK-zY4PA128erxsA5u2UZQ_LYNzmIgHIcR9R2kRkwrSEHgsa2b96p1Htu6-FN-5VzwuH7KZh7H8EPT-ICHk_ElOivtxrur_9pFz9HTGySjSX_Yux8lFQUekgU3Nn5G5bwkXGkpFReykAQiMnNFi_nCCloqJ03BNFXWKVFovtCFASNdybro9rh31zZve-dDvm72bR1P5lQbASCA8Oi6Oboq51y-a6utbQ85ASo1M4r9AE0GZ6A</recordid><startdate>20231201</startdate><enddate>20231201</enddate><creator>Chen, Wei-Jen</creator><creator>Liu, Yi-Chun</creator><creator>Chen, Yun-Wen</creator><creator>Chen, Yu-Rui</creator><creator>Lin, Hsin-Cheng</creator><creator>Tu, Chien-Te</creator><creator>Huang, Bo-Wei</creator><creator>Liu, C. W.</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><orcidid>https://orcid.org/0000-0002-1405-8639</orcidid><orcidid>https://orcid.org/0000-0002-6439-8754</orcidid><orcidid>https://orcid.org/0000-0003-2832-1853</orcidid><orcidid>https://orcid.org/0000-0002-1564-7750</orcidid><orcidid>https://orcid.org/0000-0002-2110-4867</orcidid><orcidid>https://orcid.org/0000-0002-3404-236X</orcidid></search><sort><creationdate>20231201</creationdate><title>Extremely High-κ Hf0.2Zr0.8O2 Gate Stacks Integrated Into Eight Stacked Ge0.95Si0.05 Nanowires and Nanosheets nFETs to Boost ION</title><author>Chen, Wei-Jen ; Liu, Yi-Chun ; Chen, Yun-Wen ; Chen, Yu-Rui ; Lin, Hsin-Cheng ; Tu, Chien-Te ; Huang, Bo-Wei ; Liu, C. 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W.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Extremely High-κ Hf0.2Zr0.8O2 Gate Stacks Integrated Into Eight Stacked Ge0.95Si0.05 Nanowires and Nanosheets nFETs to Boost ION</atitle><jtitle>IEEE transactions on electron devices</jtitle><stitle>TED</stitle><date>2023-12-01</date><risdate>2023</risdate><volume>70</volume><issue>12</issue><spage>6673</spage><epage>6679</epage><pages>6673-6679</pages><issn>0018-9383</issn><eissn>1557-9646</eissn><coden>IETDAI</coden><abstract><![CDATA[By taking advantage of extremely high dielectric constant (<inline-formula> <tex-math notation="LaTeX">\kappa </tex-math></inline-formula>) of 47, the Hf0.2Zr0.8O2 gate stacks are integrated into the eight stacked high mobility Ge0.95Si0.05 channels with low thermal budget (<inline-formula> <tex-math notation="LaTeX">\leqq 450 </tex-math></inline-formula> °C) to significantly enhance the <inline-formula> <tex-math notation="LaTeX">{I} _{ \mathrm{\scriptscriptstyle ON}} </tex-math></inline-formula>. Isotropic wet etching by <inline-formula> <tex-math notation="LaTeX">\text{H}_{{2}}\text{O}_{{2}} </tex-math></inline-formula> and HNO3 serve well during the channel release of nanowires and nanosheets, respectively. The simulated <inline-formula> <tex-math notation="LaTeX">\kappa </tex-math></inline-formula> versus Zr concentration in HZO can show that the <inline-formula> <tex-math notation="LaTeX">\kappa </tex-math></inline-formula> can have a peak value at Zr concentration around 80%. The eight stacked Ge0.95Si0.05 nanowires and nanosheets with Hf0.2Zr0.8O2 gate stacks achieve the record high <inline-formula> <tex-math notation="LaTeX">{I} _{ \mathrm{\scriptscriptstyle ON}} </tex-math></inline-formula> per footprint of <inline-formula> <tex-math notation="LaTeX">9200~\mu \text{A} </tex-math></inline-formula> and record high <inline-formula> <tex-math notation="LaTeX">{I} _{ \mathrm{\scriptscriptstyle ON}} </tex-math></inline-formula> per stack of <inline-formula> <tex-math notation="LaTeX">360~\mu \text{A} </tex-math></inline-formula> at <inline-formula> <tex-math notation="LaTeX">{V} _{\text {OV}} ={V}_{\text {DS}} </tex-math></inline-formula> = 0.5 V, respectively, among all Si/GeSi/Ge 3-D nFETs. Moreover, the potential gate delay improvement by combining the extremely high-<inline-formula> <tex-math notation="LaTeX">\kappa </tex-math></inline-formula> gate stacks and large floor number is studied by TCAD simulation using industrial device structures.]]></abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TED.2023.3315685</doi><tpages>7</tpages><orcidid>https://orcid.org/0000-0002-1405-8639</orcidid><orcidid>https://orcid.org/0000-0002-6439-8754</orcidid><orcidid>https://orcid.org/0000-0003-2832-1853</orcidid><orcidid>https://orcid.org/0000-0002-1564-7750</orcidid><orcidid>https://orcid.org/0000-0002-2110-4867</orcidid><orcidid>https://orcid.org/0000-0002-3404-236X</orcidid></addata></record> |
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subjects | Germanium Germanium silicon alloys GeSi high-k gate stacks highly stacked channels Logic gates Nanosheets Nanowires Silicon Stacks Wet etching Zirconium |
title | Extremely High-κ Hf0.2Zr0.8O2 Gate Stacks Integrated Into Eight Stacked Ge0.95Si0.05 Nanowires and Nanosheets nFETs to Boost ION |
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