Extremely High-κ Hf0.2Zr0.8O2 Gate Stacks Integrated Into Eight Stacked Ge0.95Si0.05 Nanowires and Nanosheets nFETs to Boost ION

By taking advantage of extremely high dielectric constant ( \kappa ) of 47, the Hf0.2Zr0.8O2 gate stacks are integrated into the eight stacked high mobility Ge0.95Si0.05 channels with low thermal budget ( \leqq 450 °C) to significantly enhance the {I} _{ \mathrm{\scriptscriptstyle ON}} . Isotropic...

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Veröffentlicht in:IEEE transactions on electron devices 2023-12, Vol.70 (12), p.6673-6679
Hauptverfasser: Chen, Wei-Jen, Liu, Yi-Chun, Chen, Yun-Wen, Chen, Yu-Rui, Lin, Hsin-Cheng, Tu, Chien-Te, Huang, Bo-Wei, Liu, C. W.
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Sprache:eng
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Zusammenfassung:By taking advantage of extremely high dielectric constant ( \kappa ) of 47, the Hf0.2Zr0.8O2 gate stacks are integrated into the eight stacked high mobility Ge0.95Si0.05 channels with low thermal budget ( \leqq 450 °C) to significantly enhance the {I} _{ \mathrm{\scriptscriptstyle ON}} . Isotropic wet etching by \text{H}_{{2}}\text{O}_{{2}} and HNO3 serve well during the channel release of nanowires and nanosheets, respectively. The simulated \kappa versus Zr concentration in HZO can show that the \kappa can have a peak value at Zr concentration around 80%. The eight stacked Ge0.95Si0.05 nanowires and nanosheets with Hf0.2Zr0.8O2 gate stacks achieve the record high {I} _{ \mathrm{\scriptscriptstyle ON}} per footprint of 9200~\mu \text{A} and record high {I} _{ \mathrm{\scriptscriptstyle ON}} per stack of 360~\mu \text{A} at {V} _{\text {OV}} ={V}_{\text {DS}} = 0.5 V, respectively, among all Si/GeSi/Ge 3-D nFETs. Moreover, the potential gate delay improvement by combining the extremely high- \kappa gate stacks and large floor number is studied by TCAD simulation using industrial device structures.
ISSN:0018-9383
1557-9646
DOI:10.1109/TED.2023.3315685