On‐chip bias‐generating architecture for an automotive application with a wide input dynamic range

This paper presents an on‐chip bias‐generating architecture for automotive applications with a wide input range of 3.8–36 V in a 0.18‐ m high‐voltage bipolar‐CMOS‐DMOS (BCD) process. The proposed architecture effectively manages high‐voltage stress issues with few high‐voltage devices optimizing the silicon area. The proposed bias‐generator comprising crude‐reference and crude‐regulator generates a preliminary low bias voltage for the bandgap‐reference circuit. An adaptive‐biased, with‐capacitor, low‐dropout regulator generates a well‐regulated core supply with low quiescent current and better stability over the wide input range. The adaptive biasing expands the unity gain frequency with increasing load enabling a fast‐transient response. The proposed LDO provides a 5‐V output voltage and a load current of 10 A to 20 mA from 5.5‐ to 36‐V supply with a 500‐mV dropout voltage consuming a very low quiescent current of 5 A. With 0‐ to 20‐mA load step and an output capacitor of 1 F, an undershoot of 40 mV and an overshoot of 55 mV are achieved.