Design of high-speed low power CMOS operational amplifier utilizing 0.18-µm technology for ADC applications

This paper presents a design of high-speed low power CMOS operational amplifier utilizing 0.18-µm technology for ADC applications. A folded cascode with PMOS configuration is chosen as a topology for the op-amp design which provides high-speed structure and more stable configuration compare to the other topologies. High-swing cascode current mirror is combined as a biasing circuit to provide proper voltage and stable output current for the op-amp structure. The proposed design is simulated in Cadence Virtuoso EDA tools software. The simulation results show the DC gain of 61.85 dB and phase margin (PM) of 88.34° with 0.5 pF load capacitor is achieved. Moreover, the slew rate and settling time of 120.125 V/µs and 20.3 ns are obtained, respectively. A low power consumption of 0.17 mW at supply voltage of 1.8 V indicates the low power is achieved in the circuit design. The proposed high speed low power CMOS op-amp is suitable for high-speed ADC applications.