A Systematic Methodology for Parasitic Capacitance Estimation and Validation of Multichip Modules

This article proposes a method for extracting parasitic capacitances from die terminals to baseplate in a multichip module. The parasitic capacitors constitute the common mode equivalent circuit model enabling filter design. While traditionally simple open module die area measurements are used to calculate capacitance from concerned nodes to baseplate, such methods result in breaking the module or contamination, rendering the module useless. This is especially concerning for high-voltage rated modules (>10 kV), where cost can be a deciding factor. Hence, a non-intrusive double pulse test method is developed to extract the parasitic capacitance from specific nodes to ground without physical damage to the module. Consequently, the proposed method is verified using a series of tests and open module measurements. The distributed capacitors can be transformed into lumped capacitors for electromagnetic compatibility simulations and filter design. The proposed method is analyzed on a three-level neutral point clamped phase leg module and compared against traditional method. Finally, the impact of estimation errors on the proposed method are discussed.