Design and Analysis of High-Performance Double Recycling Folded Cascode Operational Transconductance Amplifier

This paper presents two new refinements in a recycling folded cascode (RFC) operational transconductance amplifier (OTA) by employing a double recycling folded cascode (DRFC) structure with positive feedback. In the proposed DRFC OTA-I, unequal drain current in the two recycling stages is produced by using a floating DC voltage source, and the class AB input stage is utilized by employing a flipped voltage follower. This results in the enhancement of the transconductance and slew rate of the OTA. The positive feedback at the second recycling stage also enhances the output resistance. In the proposed DRFC OTA-II, the dynamic threshold voltage MOS (DTMOS)-based input stage of the differential pair is used to further enhance the transconductance of the proposed DRFC OTA-I. The adaptive biasing with class AB operation is also utilized in the proposed DRFC OTA-II using two cross-coupled flipped voltage followers to provide an extra boost in biasing current and further improve the slew rate. The proposed DRFC OTA-I and DRFC OTA-II also provide a high common-mode rejection ratio, low input noise, and improved phase margin. The simulation results are computed by using a supply voltage of ± 0.5 V and load of 15 pF. The proposed DRFC OTA-I and DRFC OTA-II provide DC gain of 86.42 dB and 90.75 dB with improved unity-gain bandwidth of 9.15 MHz and 11.70 MHz, respectively. To verify the robustness of the proposed DRFC OTAs, corner analysis and process–voltage–temperature (PVT) variation have been done. The simulations have been done using the Mentor Graphics Eldo tool with 0.18 µm CMOS technology.