Lowering of Schottky Barrier Height in a Vertical Pillar MOSFET by Deuterium Annealing

The Schottky barrier height (Φ B ) is lowered by high-pressure deuterium annealing (HPDA), in a vertical pillar (VP) metal-oxide-semiconductor field effect transistor (MOSFET). Typical device characteristics were comparatively studied before and after HPDA. A change of contact resistance ( R C ) at...

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Veröffentlicht in:IEEE electron device letters 2023-07, Vol.44 (7), p.1-1
Hauptverfasser: Yu, Ji-Man, Wang, Dong-Hyun, Han, Joon-Kyu, Yun, Seong-Yun, Park, Jun-Young, Choi, Yang-Kyu
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Sprache:eng
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Zusammenfassung:The Schottky barrier height (Φ B ) is lowered by high-pressure deuterium annealing (HPDA), in a vertical pillar (VP) metal-oxide-semiconductor field effect transistor (MOSFET). Typical device characteristics were comparatively studied before and after HPDA. A change of contact resistance ( R C ) at a Schottky junction was also analyzed by using a transmission line method (TLM). Moreover, HPDA effects on the R C were characterized on different crystal orientations of silicon, which has a different number of traps. HPDA is more effective to lower the Φ B at (111) orientation than at (100) orientation because a greater number of interface traps can be passivated for an orientation with a high Miller index. Finally, a deuterium peak was physically profiled across the Schottky junction by use of time-of-flight secondary ion mass spectrometry (ToF-SIMS).
ISSN:0741-3106
1558-0563
DOI:10.1109/LED.2023.3281856