Design of Ternary Multiplier Using Pseudo NCNTFETs

A novel technique is proposed in this paper to design ternary logic circuits for nanoelectronics applications. The ternary logic is a best alternative to the binary logic because it offers reduced interconnects, faster operating speed and reduced chip area. The digital multiplier circuit is developed using Pseudo n -type carbon nanotube field effect transistors (CNTFETs). The ternary inverter circuits, basic gates and decoder circuits are used to develop the proposed multiplier. The proposed ternary multiplier is designed and simulated using the HSPICE simulator. Moreover, the performance of the proposed multiplier circuit is investigated in terms of delay, power dissipation and power delay product (PDP) and compared with the complementary based multiplier circuits. It is noticed that the proposed multiplier shows high performance up to 31.42% over the complementary based multiplier circuits.