A New Design of Multilevel Inverter Based on T-type Symmetrical and Asymmetrical DC Sources

The aim of this paper to propose a new topology of multilevel inverter (MLI) for both the cases symmetrical as well as an asymmetrical magnitude of DC sources for grid-tied applications. A basic module generates 9-level voltage output in symmetrical mode, 15-level output voltage in asymmetrical mode (binary fashion) and output voltage of 21-level in asymmetrical mode (trinary fashion). The basic module consists of 11 switches (10 unidirectional switches and 1 bidirectional switch) with two PV sources having unequal magnitudes. The new design of proposed MLI reduces the number of switches, PV sources significantly as compared to other MLI topologies. In comparison with traditional MLI topologies, the proposed MLI topology has minimal conduction and switching losses. Furthermore, the module has been tested, and the results have shown that it performs well in dynamic environments. The output voltage waveforms of the different inverters, i.e., 9-level, 15-level, and 21-level, had total harmonic distortion (THD) of 9.11%, 5.28%, and 3.67%, accordingly. Moreover, the efficiency of the different inverters, i.e., 9-level, 15-level, and 21-level, is about than 98% for the different output powers (80–1380 W). A single-phase 9-level, 15-level, and 21-level prototype inverter is used to implement the new proposed design through simulation and hardware development. The dSPACE real-time controller is used to generate switching signals using a pulse-width modulation-based multicarrier technique. In terms of the number of switches, on-state switches, and gate driver circuits, a comparison is made with various multilevel inverter topologies. The comparison results showed that for the same number of voltage levels, the new recommended configuration needed fewer components. The authors suggest a new topology for an asymmetrical arrangement in this paper. Simulation and experimental implementation are used to evaluate the performance of the new suggested topology under steady-state and dynamic state situations.