High-throughput and low-latency ASIC implementation of lightweight cryptography

This paper presents high throughput and low latency ASIC implementation of a lightweight cryptography. Most of the lightweight algorithms are round-based design, whereby the high-throughput is achieved via the pipeline of the round functions. However, the response time is not ideal as such algorithms were designed crucially on area based. The PRINCE cipher is developed to speed up the latency of the algorithm while managing a competitive area utilization. Therefore, it is a promising choice for low-resource devices that emphasize response time. In this work, the PRINCE cipher is designed and synthesized in a single-cycle, reduced multi cycle, and compared with the round-per-cycle implementation as a baseline. The synthesis results reveal that the single-cycle PRINCE cipher is achievable with an almost 40% reduction in encryption latency. Further analysis on optimization of RTL designs and data path constraints have also been carried out to improve the implementation in term of gate count, delay, and power consumption, which is based on a 32nm SAED Cell Library using Synopsys tools.