Design of a low power high-speed dynamic latched comparator in 65- nm CMOS using peaking techniques

This paper presents a new low-power, high-speed double-tail dynamic latched comparator with a novel pre-amplifier stage using peaking techniques approach in the design structure. Peaking is achieved for high frequency applications by connecting a negative capacitance in parallel with the output load capacitance of the pre-amplifier stage. Here, the negative capacitance can be realized by using a negative impedance converter (NIC) based on a cross-coupled nMOS latch circuit. This allows, to tune out surplus load capacitance and the bandwidth can be extended in the frequency domain. Consequently, both power consumption and delay time are reduced, the proposed circuit is designed in Ansys Electronics Suite and simulated with HSPICE using 65 nm TSMC technology node. For 1 V of supply voltage, at a clock frequency of 18 GHz with a differential input voltage ( Δ Vin) of 25 mV, the simulation results reveal that the delay and average power consumption of the proposed dynamic comparator are 13.16 ps and 241 μ W respectively with 3.18fJ as energy per comparison.