Implementation of FPGA based hardware/software co-design SoC for median filter

Nowadays, video and image processing has become the vital part of the system used in each and every field such as medical, Military, Security etc Generally pre-processing filtering is the first and most important task in the systems, hence the speed of the filters is an important parameter. As the Median filter is a nonlinear digital filter often used to reduce the random noise especially Salt and pepper noise from images without damaging the edges, and it is also used for background estimation in video surveillance. In this project a new code for implementation of median filter based on efficient hardware/software co-design is introduced and applied to image filtering problems. In this design the implementation of the hardware and software is achieved simultaneously on programmable chip. The software implementation is achieved using NIOS-II and microClinux as operating system. And hardware part is implemented on EP4CE115F29I8L FPGA device. The execution time of the whole filtering process is evaluated and part of process having higher execution time is implemented on hardware. The results of the software solution alone, and hardware solution alone, the software / hardware co-design solution are reported and compared, emphasizing the computation speed.