Improved dynamic performance with discrete sampling in digital ACM controlled DC‐DC boost converter with capacitor ESR inclusion

A classical symmetrical carrier‐based digital Average Current Mode (ACM) control has two sampling choices, peak point and valley point, to control the average inductor current. If it is employed to regulate the DC‐DC boost converter, there will be a difference in the dynamic performance at peak and valley point sampling instants because of discontinuous output voltage ripple due to Equivalent Series Resistance (ESR) of the output capacitor. Therefore, this paper investigates the effect of sampling instant on the dynamic performance of the PWM DC‐DC boost converter in consideration of capacitor ESR. The small‐signal transfer functions of a boost converter for both sampling positions are prominent to analyze each sampling impact on its dynamics. They are derived by using discrete‐time modeling. Further, the choices of sampling instant are investigated related to the RHP zero elimination, voltage stability, and peak‐to‐peak ripple current of the DC‐DC boost converter. The boost converter has improved stability performance by synchronizing the ADC sampling at starting position (valley point) of the symmetrical carrier signal, as evident by the analytical and hardware results of both sampling techniques working from 25% to 100% load working conditions. In the proposed work, detailed analysis with an application‐oriented approach has been provided in both frequency‐ and time‐domain approaches to effectively understand the effect of sampling position on a digitally controlled DC‐DC boost converter. It is proven that the sampling location of the control variable must be precisely synchronized with the starting position of the carrier signal to ensure the proper functioning of a digitally controlled boost converter.