Class‐F power oscillator based on complementary split ring resonator for sub‐6 GHz fifth generation and multistandard applications

Summary A coupled complementary split‐ring resonator (CSRR) has been proposed. The proposed resonator consists of two coupled 50‐Ω transmission lines and complementary split rings in the ground plane (bottom layer) as defected ground structure (DGS). The proposed bandpass filter (BPF) has a measured stopband attenuation loss of less than −20 dB in the frequency band between 2.3 and 2.9 GHz and a low insertion loss of 1.15 dB. The measurement is carried by a VNA (vector network analyzer) meter of model ZVA67. Then, the proposed resonator (BPF) is utilized with an active device (SiGe BFP 640) as an output matching network of a class‐F oscillator. Fundamentally, this research aims to design and model an optimum achievement of BPF for optimum oscillator performance. The design simulation of the CSRR oscillator has been obtained by ADS and CST programs. The proposed band pass filter is designed and fabricated on a Rogers (RO4003C) micro‐strip material printed with a dielectric constant epsilon of 3.38 and a thickness of 0.813 mm. Depending on this study, the oscillator displays a minimum phase noise of −109.3 dBc/Hz at 1 MHz offset frequency and maximum dBm output power equals 13.4 dBm at 2.45 GHz oscillation frequency. The power dispassion of the proposed oscillator equals 8.3 mW from a 2 V supply voltage. The obtained maximum dBm output power and minimum phase noise is a benefit for power charger wireless applications, sub‐6 GHz fifth generation applications, and multistandard applications. The suggested class‐F oscillator schematic composes of an Infineon BFP640 bipolar transistor, a high selectivity coupled CSRR filter, and a feedback network (embedding network). The feedback network is designed to accept the Barkhausen criteria on oscillation conditions and to obtain the best achievement. To achieve the best phase noise performance, the oscillation frequency is set at the highest group delay span region. The initial step of the design is to choose a DC operating point for the radio frequency transistor. The objective was to choose an operating point that would afford sufficient output power, have proportionally low noise, and work in the class‐F operation. Figure illustrates the schematic circuit of the suggested harmonic‐tuned radio frequency oscillator. It composes of the transistor (BFP640), feedback (C1, L1), load (RL), and harmonics networks (third harmonics [C3, L3] and second harmonics [C2, L2]). Various LC resonators are utilized to permit the inde