Reducing Subsurface Damage with Trizact™ Diamond Tile During a Prime Silicon Wafer Grinding Process

Optimizing key components of Trizact™ Diamond Tile can significantly reduce subsurface damage (SSD) in a prime silicon wafer lapping (or grinding) process. It is proposed that with this SSD reduction, a conventional prime wafer finishing sequence can be improved either by eliminating an entire step or by materially reducing subsequent polishing requirements. Experiments using 100 mm silicon wafers showed a reduction in maximum SSD from over 6 µm to about 2.5 µm in depth. Correlations with production 300 mm wafers suggest that this reduction should result in SSD well under 8 µm for 300 mm prime silicon wafers. Graphical Abstract