Dielectric Interface Engineering for High-Performance Monolayer MoS2 Transistors via TaOxInterfacial Layer

Field-effect transistors (FETs) based on 2-D materials have great potential for future ultimate-scaled electronics. However, nonideal semiconductor–dielectric interfaces due to interfacial traps and oxide traps have constrained the potential of 2-D semiconductors. Here, we report a new dielectric interface engineering approach for monolayer (1L) MoS2 transistors employing a relatively high-[Formula Omitted] TaOx interfacial layer ([Formula Omitted]7) whose defect bands are located outside of the operation window of the MoS2 Fermi level. Such band alignment can minimize active interface trap states in top-gate (TG) dielectric stacks. The TaOx interfacial layer can also act as an efficient doping layer, with the highest ON-current [Formula Omitted] reaching 861 [Formula Omitted] at [Formula Omitted] = 1.5 V and overdrive voltage [Formula Omitted] = 3 V. The lowest contact resistance is down to [Formula Omitted]. Dual-gate (DG) FETs can achieve subthreshold slope (SS) values down to [Formula Omitted]70 mV/dec in short-channel devices ([Formula Omitted]–75 nm). Our reported SS, [Formula Omitted], and [Formula Omitted] are among the best-reported values for MoS2 devices. For low-power applications, our devices exhibit a record-high [Formula Omitted] of 598 [Formula Omitted] at [Formula Omitted] V. The new dielectric engineering approach proposed in this study can pave the way for realizing high-performance logic devices based on 2-D materials.