Design and Analysis of a Symmetrical Low-κ Source-Side Spacer Multi-gate Nanowire Device

In this paper, we propose a symmetrical low-κ source-side spacer multi-gate nanowire device design and analysis. High-κ spacer materials are currently researched extensively for improving electrostatic control and suppressing short-channel effects in nanoscale electronics. However, the excessive increase in fringe capacitance of high-κ spacers degrades the dynamic circuit performance. Surprisingly, this approach achieves a significant reduction in gate capacitance by maximizing the use of high-κ spacer material. Three different structures, a symmetrical dual-κ spacer, symmetrical low-κ drain-side spacer, and symmetrical low-κ source-side spacer multi-gate nanowire MOSFET, are simulated, and the symmetrical low-κ source-side spacer multi-gate nanowire device is found to achieve lower gate capacitance. Simulations performed in Silvaco TCAD showed drain current (I d ) of 4.9 A/mm, OFF-current (I off) of 9.54 × 10 −12 A, transconductance (g m ) of 2.7 S/mm at V gs = −0.4 V, cutoff frequency (f T ) of 560 GHz, drain conductance (g d ) of 0.657 S/mm, and ON-resistance ( R on ) of 0.6 ohm mm The proposed structure is thus applicable for next-generation terahertz/millimeter wave high-power applications and thus is highly recommended for digital applications.