Bus-Aware IO Alignment Considering Length-Matching Constraints in 3-D IC Designs

It is known that input/output (IO) alignment between two stacking dies plays an important role in three-dimensional (3-D) integrated circuit (IC) designs. In this article, given a set of nets with some buses considering length-matching constraints and a set of micro-bumps on two adjacent redistribut...

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Veröffentlicht in:	IEEE transactions on components, packaging, and manufacturing technology (2011) packaging, and manufacturing technology (2011), 2023-01, Vol.13 (1), p.79-92
1. Verfasser:	Yan, Jin-Tai
Format:	Artikel
Sprache:	eng
Schlagworte:	3-D integrated circuit (IC) designs Algorithms Alignment Central processing units Circuit design CPUs input/output (IO) alignment Integrated circuits Matching micro-bump assignment Minimization Pins redistributed layer (RDL) routing Routing Stacking Three-dimensional displays Through-silicon vias Voronoi graphs
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