Bus-Aware IO Alignment Considering Length-Matching Constraints in 3-D IC Designs

It is known that input/output (IO) alignment between two stacking dies plays an important role in three-dimensional (3-D) integrated circuit (IC) designs. In this article, given a set of nets with some buses considering length-matching constraints and a set of micro-bumps on two adjacent redistributed layers (RDLs), an efficient algorithm can be proposed for bus-aware IO alignment with length-matching constraints in 3-D IC designs. First, based on the planar routability of using Voronoi diagrams in single-layer routing and the definition of the capacity constraint on local regions in a routing plane, the given nets can be assigned onto some available micro-bumps for wirelength minimization in bus-aware micro-bump assignment (BMBA). Furthermore, based on the net grouping inside some extracted regions in single-layer RDL routing (SRDLR) and the length constraint of some in-bus nets, the assigned partial nets on two adjacent RDLs can be routed and some zigzag paths can be iteratively inserted onto the routing paths of the in-bus nets to minimize the maximum skew of the given buses in RDL routing under length-matching constraints. Compared with Kuan's modified algorithm, Yan's modified algorithm, and Zhang's modified algorithm, the experimental results show that our proposed algorithm can use reasonable central processing unit (CPU) time to reduce 11.5%, 9.0%, and 6.8% of the total wirelength on 100% routability for eight tested examples on the average. In addition, based on the near 100% routability or eight denser tested examples in our proposed algorithm, the experimental results show that our proposed algorithm can use reasonable CPU time to increase 3.3%, 3.4%, and 4.0% of routability on two adjacent RDLs for eight denser tested examples on the average.