Design and readout architecture of a monolithic binary active pixel sensor in TPSCo 65 nm CMOS imaging technology

The Digital Pixel Test Structure (DPTS) is a monolithic active pixel sensor prototype chip designed to explore the TPSCo 65 nm ISC process in the framework of the CERN-EP R&D on monolithic sensors and the ALICE ITS3 upgrade. It features a 32 × 32 binary pixel matrix at 15 μm pitch with event-driven readout, with GHz range time-encoded digital signals including Time-Over-Threshold. The chip proved fully functional and efficient in testbeam allowing early verification of the complete sensor to readout chain. This paper focuses on the design, in particular the digital readout and its perspectives with some supporting results.