C-DMR: a cache-based fault-tolerant protection method for register file

The processor in the space environment is susceptible to the interference of high-energy particles, resulting in abnormal operation of the processor. These processors require fault-tolerant designs to handle various disturbances in the environment. In this paper, we propose a cache-based fault-tolerant protection method for the register file and we implement it in a RISC-V processor on the FPGA platform. This method uses spatial redundancy and information redundancy to reduce the propagation of single-bit errors, and it can resolve potential fault accumulation issues in the register file. Compared with other methods for register files, the proposed implementation has advantages in resource consumption by reusing the inherent data cache structure in the processor, only increasing 76% look-up tables and causing 6.09% extra delay. Finally, we evaluate the impact on system performance after removing some cachelines from the data cache and get conclusion that this design improves the processor’s fault tolerance with small impact on the original data cache performance.