A Polynomial Transform Method for Hardware Systematic Error Identification and Correction in Semiconductor Multi-Site Testing

Multi-site measurement (testing) increases throughput and reduces production test costs by simultaneously testing multiple chips. However, as the number of test sites is increased (to maximize throughput further), site-to-site variation in analog and mixed-signal circuits test measurement inevitably increases to levels causing mis-trim and/or misclassification of the device under test (DUT). This work proposes a practical and low-cost approach to effectively identify and correct pronounced site-to-site variation inherent in multi-site test data. Assuming the test hardware is stationary or time-invariant, the measured chip parameter at a site is modeled as a weak nonlinear function of the true parameter for that site. A polynomial transform-based method is proposed to identify this systematic nonlinearity. The approximate inverse function of the identified nonlinearity is then applied to the measurements at the issue sites to remove the effect of the induced hardware systematic errors. This approach is practical and cost-effective as it enables continued use of existing hardware, avoids expensive root-cause analysis, and re-fabrication of multi-site test boards. It improves yield by achieving more accurate chip measurements and reduces test escapes. The accuracy and robustness of the method are confirmed after application to simulated and real-world industrial test data.