Pathfinder Algorithm Modification for FPGA Routing Stage

One of the main advantages of FPGA design flow is the high development speed; therefore, the importance of effective computer-aided design tools for modern microcircuits of these classes cannot be overestimated. Placement and routing are the most time-consuming stages of FPGA design flow. The quality of results of these stages is crucial to the final performance of custom digital circuits implemented on FPGA. The paper discusses an approach to accelerating the routing stage within the layout synthesis flow for FPGA by introducing a few algorithmic improvements to a routing procedure. The basic routing algorithm under study is a modified Pathfinder for a mixed routing resources graph. Pathfinder is a well-known negotiation-based routing algorithm that works on the principle of iteratively eliminating congestions of chip routing resources. The sets of test digital circuits ISCAS’85, ISCAS’89, LGSynth’89 and several custom industrial projects were used for computational experiments. The impact of the proposed algorithmic improvements was analyzed using four FPGA architectures. It has been established that due to the improvements of the algorithm proposed in the paper, the average reduction in routing time was from 1.3 to 2.6 times, depending on the FPGA architecture, with no significant negative effect on the timing characteristics of the designed circuits.