Design and Development of High Voltage High Pulse Power Supply using FPGA for Dynamic Impedance Matching

High Voltage High Pulse Power Supply (HVHPPS) is designed with the goal to match fixed load, so thatprecise pulse output can be achieved. Generally the loads involve magnetron, klystron, and particle accelerators etc. The HVHPPS output pulse shape changes with load impedance variation due to various...

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Veröffentlicht in:Defense science journal 2022-11, Vol.72 (6), p.873-880
Hauptverfasser: Rai, Krishna Kumar, Giridhar, AV, Jahagirdar, D.R., Rai, Ashish
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Sprache:eng
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Zusammenfassung:High Voltage High Pulse Power Supply (HVHPPS) is designed with the goal to match fixed load, so thatprecise pulse output can be achieved. Generally the loads involve magnetron, klystron, and particle accelerators etc. The HVHPPS output pulse shape changes with load impedance variation due to various reasons. Due to changes in impedance, the performance of Pulse Power Supply degrades and reflects the power at the source end which causes component failure and system shut down. To overcome such problems, a scale down High Voltage High Pulse Power is designed and developed to match the dynamic impedance variations upto 25 % of mismatch. In earlier days, all HVHPPS were designed using microcontrollers where the problem of pulse to pulse monitoring and computational speed was compromised. The availability of variable and self-defined, Field Programmable Gate Array (FPGA) controller, which provided flexibility to design the pulse to pulse shaping and various vital parameter monitoring, made it possible. This paper presents the design and implementation of HVHPPS over an FPGA platform to meet the fast response requirement. This paper provides a solution for impedance mismatch problems associated with such types of power supply, and also presents specifications for major components in a high voltage pulse power system for various types of load ranges. An experimental test hardware was designed and developed for HVHPPS to implement dynamic impedance algorithm and validate the results.
ISSN:0011-748X
0976-464X
DOI:10.14429/dsj.72.18165