A 16-Gb T-Coil-Based GDDR6 DRAM With Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus Achieving 27-Gb/s/Pin in NRZ
This article introduces a 16-Gb T-coil-based graphics double-data-rate 6 (GDDR6) dynamic random access memory (DRAM) with merged-multiplexer (MUX) transmitter (TX), optimized data clock (WCK) operation to enhance I/O bandwidth. T-coil is implemented for the first time in a DRAM process. Moreover, an...
Gespeichert in:
| Veröffentlicht in: | IEEE journal of solid-state circuits 2023-01, Vol.58 (1), p.279-290 |
|---|---|
| Hauptverfasser: | , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , |
| Format: | Artikel |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | 290 |
|---|---|
| container_issue | 1 |
| container_start_page | 279 |
| container_title | IEEE journal of solid-state circuits |
| container_volume | 58 |
| creator | Lee, Daewoong Baek, Jaehyeok Kwon, Hye-Jung Kwon, Dae-Hyun Cho, Chulhee Kim, Sang-Hoon An, Donggun Chang, Chulsoon Lim, Unhak Im, Jiyeon Sung, Wonju Kim, Hye-Ran Park, Sun-Young Kim, Hyoung-Joo Seol, Hoseok Kim, Juhwan Shin, Jungbum Kang, Gil-Young Kim, Yong-Hun Kim, Sooyoung Park, Wansoo Kim, Seok-Jung Lee, Chan-Yong Lee, Seungseob Park, Tae-Hoon Oh, Chi-Sung Ban, Hyodong Ko, Hyungjong Song, Hoyoung Oh, Tae-Young Hwang, Sang-Joon Oh, Kyung-Suk Choi, Jung-Hwan Lee, Jooyoung |
| description | This article introduces a 16-Gb T-coil-based graphics double-data-rate 6 (GDDR6) dynamic random access memory (DRAM) with merged-multiplexer (MUX) transmitter (TX), optimized data clock (WCK) operation to enhance I/O bandwidth. T-coil is implemented for the first time in a DRAM process. Moreover, an alternative-data-bus (ADB) is employed to solve the frequency limit of the data bus. The proposed T-coil-based GDDR6 DRAM achieves 27 Gb/s/pin with 1.35 V in a DRAM process. |
| doi_str_mv | 10.1109/JSSC.2022.3222203 |
| format | Article |
| fullrecord | <record><control><sourceid>proquest_RIE</sourceid><recordid>TN_cdi_proquest_journals_2758722715</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>9968075</ieee_id><sourcerecordid>2758722715</sourcerecordid><originalsourceid>FETCH-LOGICAL-c293t-630f63dc674eb122c6bfbbfab76e03463a418319c28490f2296c7cff1ae541523</originalsourceid><addsrcrecordid>eNo9kFtLwzAUx4MoOKcfQHwJ-Gq2XNqkfexanZfNyS5s-FLSNt0yunY23UAf_eRmbHg4cPgffufCH4BbgjuEYL_7OpmEHYop7TBqA7Mz0CKu6yEi2OIctDAmHvIpxpfgypi1lY7jkRb4DSDhqJ_AKQorXaCeNCqD_SgacxiNgyGc62YFh6peqgwNZws4XTzA0bbRG_1jwXn4ZpWqZaOr8gHKMoNB0ai6tI29QpFsJOrtDAzSlVZ7XS4hFfZa13Q_dAltvo8_r8FFLgujbk61DWZPj9PwGQ1G_ZcwGKCU-qxBnOGcsyzlwlEJoTTlSZ4kuUwEV5g5nEmHeIz4KfUcH-eU-jwVaZ4TqVyHuJS1wf1x77auvnbKNPG62tlPCxNT4XqCUkFcS5EjldaVMbXK422tN7L-jgmOD1bHB6vjg9XxyWo7c3ec0Uqpf973uYeFy_4AwZZ1Sw</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>2758722715</pqid></control><display><type>article</type><title>A 16-Gb T-Coil-Based GDDR6 DRAM With Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus Achieving 27-Gb/s/Pin in NRZ</title><source>IEEE/IET Electronic Library (IEL)</source><creator>Lee, Daewoong ; Baek, Jaehyeok ; Kwon, Hye-Jung ; Kwon, Dae-Hyun ; Cho, Chulhee ; Kim, Sang-Hoon ; An, Donggun ; Chang, Chulsoon ; Lim, Unhak ; Im, Jiyeon ; Sung, Wonju ; Kim, Hye-Ran ; Park, Sun-Young ; Kim, Hyoung-Joo ; Seol, Hoseok ; Kim, Juhwan ; Shin, Jungbum ; Kang, Gil-Young ; Kim, Yong-Hun ; Kim, Sooyoung ; Park, Wansoo ; Kim, Seok-Jung ; Lee, Chan-Yong ; Lee, Seungseob ; Park, Tae-Hoon ; Oh, Chi-Sung ; Ban, Hyodong ; Ko, Hyungjong ; Song, Hoyoung ; Oh, Tae-Young ; Hwang, Sang-Joon ; Oh, Kyung-Suk ; Choi, Jung-Hwan ; Lee, Jooyoung</creator><creatorcontrib>Lee, Daewoong ; Baek, Jaehyeok ; Kwon, Hye-Jung ; Kwon, Dae-Hyun ; Cho, Chulhee ; Kim, Sang-Hoon ; An, Donggun ; Chang, Chulsoon ; Lim, Unhak ; Im, Jiyeon ; Sung, Wonju ; Kim, Hye-Ran ; Park, Sun-Young ; Kim, Hyoung-Joo ; Seol, Hoseok ; Kim, Juhwan ; Shin, Jungbum ; Kang, Gil-Young ; Kim, Yong-Hun ; Kim, Sooyoung ; Park, Wansoo ; Kim, Seok-Jung ; Lee, Chan-Yong ; Lee, Seungseob ; Park, Tae-Hoon ; Oh, Chi-Sung ; Ban, Hyodong ; Ko, Hyungjong ; Song, Hoyoung ; Oh, Tae-Young ; Hwang, Sang-Joon ; Oh, Kyung-Suk ; Choi, Jung-Hwan ; Lee, Jooyoung</creatorcontrib><description>This article introduces a 16-Gb T-coil-based graphics double-data-rate 6 (GDDR6) dynamic random access memory (DRAM) with merged-multiplexer (MUX) transmitter (TX), optimized data clock (WCK) operation to enhance I/O bandwidth. T-coil is implemented for the first time in a DRAM process. Moreover, an alternative-data-bus (ADB) is employed to solve the frequency limit of the data bus. The proposed T-coil-based GDDR6 DRAM achieves 27 Gb/s/pin with 1.35 V in a DRAM process.</description><identifier>ISSN: 0018-9200</identifier><identifier>EISSN: 1558-173X</identifier><identifier>DOI: 10.1109/JSSC.2022.3222203</identifier><identifier>CODEN: IJSCBC</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Alternative-data-bus (ADB) ; Bandwidth ; Clocks ; Coils ; data clock (WCK) ; Dynamic random access memory ; Graphics ; graphics double-data-rate 6 (GDDR6) ; graphics dynamic random access memory (DRAM) ; high-speed memory ; Load modeling ; merged-multiplexer (MUX) transmitter (TX) ; Metals ; quad-skew training ; Random access memory ; reference impedance (ZQ) calibration ; Resistance ; T-coil ; wireline transceiver</subject><ispartof>IEEE journal of solid-state circuits, 2023-01, Vol.58 (1), p.279-290</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2023</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c293t-630f63dc674eb122c6bfbbfab76e03463a418319c28490f2296c7cff1ae541523</citedby><cites>FETCH-LOGICAL-c293t-630f63dc674eb122c6bfbbfab76e03463a418319c28490f2296c7cff1ae541523</cites><orcidid>0000-0001-8703-2627 ; 0000-0002-9379-7746 ; 0000-0003-4651-2434 ; 0000-0003-3507-2613 ; 0000-0002-3611-4734</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/9968075$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,776,780,792,27901,27902,54733</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/9968075$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Lee, Daewoong</creatorcontrib><creatorcontrib>Baek, Jaehyeok</creatorcontrib><creatorcontrib>Kwon, Hye-Jung</creatorcontrib><creatorcontrib>Kwon, Dae-Hyun</creatorcontrib><creatorcontrib>Cho, Chulhee</creatorcontrib><creatorcontrib>Kim, Sang-Hoon</creatorcontrib><creatorcontrib>An, Donggun</creatorcontrib><creatorcontrib>Chang, Chulsoon</creatorcontrib><creatorcontrib>Lim, Unhak</creatorcontrib><creatorcontrib>Im, Jiyeon</creatorcontrib><creatorcontrib>Sung, Wonju</creatorcontrib><creatorcontrib>Kim, Hye-Ran</creatorcontrib><creatorcontrib>Park, Sun-Young</creatorcontrib><creatorcontrib>Kim, Hyoung-Joo</creatorcontrib><creatorcontrib>Seol, Hoseok</creatorcontrib><creatorcontrib>Kim, Juhwan</creatorcontrib><creatorcontrib>Shin, Jungbum</creatorcontrib><creatorcontrib>Kang, Gil-Young</creatorcontrib><creatorcontrib>Kim, Yong-Hun</creatorcontrib><creatorcontrib>Kim, Sooyoung</creatorcontrib><creatorcontrib>Park, Wansoo</creatorcontrib><creatorcontrib>Kim, Seok-Jung</creatorcontrib><creatorcontrib>Lee, Chan-Yong</creatorcontrib><creatorcontrib>Lee, Seungseob</creatorcontrib><creatorcontrib>Park, Tae-Hoon</creatorcontrib><creatorcontrib>Oh, Chi-Sung</creatorcontrib><creatorcontrib>Ban, Hyodong</creatorcontrib><creatorcontrib>Ko, Hyungjong</creatorcontrib><creatorcontrib>Song, Hoyoung</creatorcontrib><creatorcontrib>Oh, Tae-Young</creatorcontrib><creatorcontrib>Hwang, Sang-Joon</creatorcontrib><creatorcontrib>Oh, Kyung-Suk</creatorcontrib><creatorcontrib>Choi, Jung-Hwan</creatorcontrib><creatorcontrib>Lee, Jooyoung</creatorcontrib><title>A 16-Gb T-Coil-Based GDDR6 DRAM With Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus Achieving 27-Gb/s/Pin in NRZ</title><title>IEEE journal of solid-state circuits</title><addtitle>JSSC</addtitle><description>This article introduces a 16-Gb T-coil-based graphics double-data-rate 6 (GDDR6) dynamic random access memory (DRAM) with merged-multiplexer (MUX) transmitter (TX), optimized data clock (WCK) operation to enhance I/O bandwidth. T-coil is implemented for the first time in a DRAM process. Moreover, an alternative-data-bus (ADB) is employed to solve the frequency limit of the data bus. The proposed T-coil-based GDDR6 DRAM achieves 27 Gb/s/pin with 1.35 V in a DRAM process.</description><subject>Alternative-data-bus (ADB)</subject><subject>Bandwidth</subject><subject>Clocks</subject><subject>Coils</subject><subject>data clock (WCK)</subject><subject>Dynamic random access memory</subject><subject>Graphics</subject><subject>graphics double-data-rate 6 (GDDR6)</subject><subject>graphics dynamic random access memory (DRAM)</subject><subject>high-speed memory</subject><subject>Load modeling</subject><subject>merged-multiplexer (MUX) transmitter (TX)</subject><subject>Metals</subject><subject>quad-skew training</subject><subject>Random access memory</subject><subject>reference impedance (ZQ) calibration</subject><subject>Resistance</subject><subject>T-coil</subject><subject>wireline transceiver</subject><issn>0018-9200</issn><issn>1558-173X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2023</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kFtLwzAUx4MoOKcfQHwJ-Gq2XNqkfexanZfNyS5s-FLSNt0yunY23UAf_eRmbHg4cPgffufCH4BbgjuEYL_7OpmEHYop7TBqA7Mz0CKu6yEi2OIctDAmHvIpxpfgypi1lY7jkRb4DSDhqJ_AKQorXaCeNCqD_SgacxiNgyGc62YFh6peqgwNZws4XTzA0bbRG_1jwXn4ZpWqZaOr8gHKMoNB0ai6tI29QpFsJOrtDAzSlVZ7XS4hFfZa13Q_dAltvo8_r8FFLgujbk61DWZPj9PwGQ1G_ZcwGKCU-qxBnOGcsyzlwlEJoTTlSZ4kuUwEV5g5nEmHeIz4KfUcH-eU-jwVaZ4TqVyHuJS1wf1x77auvnbKNPG62tlPCxNT4XqCUkFcS5EjldaVMbXK422tN7L-jgmOD1bHB6vjg9XxyWo7c3ec0Uqpf973uYeFy_4AwZZ1Sw</recordid><startdate>20230101</startdate><enddate>20230101</enddate><creator>Lee, Daewoong</creator><creator>Baek, Jaehyeok</creator><creator>Kwon, Hye-Jung</creator><creator>Kwon, Dae-Hyun</creator><creator>Cho, Chulhee</creator><creator>Kim, Sang-Hoon</creator><creator>An, Donggun</creator><creator>Chang, Chulsoon</creator><creator>Lim, Unhak</creator><creator>Im, Jiyeon</creator><creator>Sung, Wonju</creator><creator>Kim, Hye-Ran</creator><creator>Park, Sun-Young</creator><creator>Kim, Hyoung-Joo</creator><creator>Seol, Hoseok</creator><creator>Kim, Juhwan</creator><creator>Shin, Jungbum</creator><creator>Kang, Gil-Young</creator><creator>Kim, Yong-Hun</creator><creator>Kim, Sooyoung</creator><creator>Park, Wansoo</creator><creator>Kim, Seok-Jung</creator><creator>Lee, Chan-Yong</creator><creator>Lee, Seungseob</creator><creator>Park, Tae-Hoon</creator><creator>Oh, Chi-Sung</creator><creator>Ban, Hyodong</creator><creator>Ko, Hyungjong</creator><creator>Song, Hoyoung</creator><creator>Oh, Tae-Young</creator><creator>Hwang, Sang-Joon</creator><creator>Oh, Kyung-Suk</creator><creator>Choi, Jung-Hwan</creator><creator>Lee, Jooyoung</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><orcidid>https://orcid.org/0000-0001-8703-2627</orcidid><orcidid>https://orcid.org/0000-0002-9379-7746</orcidid><orcidid>https://orcid.org/0000-0003-4651-2434</orcidid><orcidid>https://orcid.org/0000-0003-3507-2613</orcidid><orcidid>https://orcid.org/0000-0002-3611-4734</orcidid></search><sort><creationdate>20230101</creationdate><title>A 16-Gb T-Coil-Based GDDR6 DRAM With Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus Achieving 27-Gb/s/Pin in NRZ</title><author>Lee, Daewoong ; Baek, Jaehyeok ; Kwon, Hye-Jung ; Kwon, Dae-Hyun ; Cho, Chulhee ; Kim, Sang-Hoon ; An, Donggun ; Chang, Chulsoon ; Lim, Unhak ; Im, Jiyeon ; Sung, Wonju ; Kim, Hye-Ran ; Park, Sun-Young ; Kim, Hyoung-Joo ; Seol, Hoseok ; Kim, Juhwan ; Shin, Jungbum ; Kang, Gil-Young ; Kim, Yong-Hun ; Kim, Sooyoung ; Park, Wansoo ; Kim, Seok-Jung ; Lee, Chan-Yong ; Lee, Seungseob ; Park, Tae-Hoon ; Oh, Chi-Sung ; Ban, Hyodong ; Ko, Hyungjong ; Song, Hoyoung ; Oh, Tae-Young ; Hwang, Sang-Joon ; Oh, Kyung-Suk ; Choi, Jung-Hwan ; Lee, Jooyoung</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c293t-630f63dc674eb122c6bfbbfab76e03463a418319c28490f2296c7cff1ae541523</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2023</creationdate><topic>Alternative-data-bus (ADB)</topic><topic>Bandwidth</topic><topic>Clocks</topic><topic>Coils</topic><topic>data clock (WCK)</topic><topic>Dynamic random access memory</topic><topic>Graphics</topic><topic>graphics double-data-rate 6 (GDDR6)</topic><topic>graphics dynamic random access memory (DRAM)</topic><topic>high-speed memory</topic><topic>Load modeling</topic><topic>merged-multiplexer (MUX) transmitter (TX)</topic><topic>Metals</topic><topic>quad-skew training</topic><topic>Random access memory</topic><topic>reference impedance (ZQ) calibration</topic><topic>Resistance</topic><topic>T-coil</topic><topic>wireline transceiver</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Lee, Daewoong</creatorcontrib><creatorcontrib>Baek, Jaehyeok</creatorcontrib><creatorcontrib>Kwon, Hye-Jung</creatorcontrib><creatorcontrib>Kwon, Dae-Hyun</creatorcontrib><creatorcontrib>Cho, Chulhee</creatorcontrib><creatorcontrib>Kim, Sang-Hoon</creatorcontrib><creatorcontrib>An, Donggun</creatorcontrib><creatorcontrib>Chang, Chulsoon</creatorcontrib><creatorcontrib>Lim, Unhak</creatorcontrib><creatorcontrib>Im, Jiyeon</creatorcontrib><creatorcontrib>Sung, Wonju</creatorcontrib><creatorcontrib>Kim, Hye-Ran</creatorcontrib><creatorcontrib>Park, Sun-Young</creatorcontrib><creatorcontrib>Kim, Hyoung-Joo</creatorcontrib><creatorcontrib>Seol, Hoseok</creatorcontrib><creatorcontrib>Kim, Juhwan</creatorcontrib><creatorcontrib>Shin, Jungbum</creatorcontrib><creatorcontrib>Kang, Gil-Young</creatorcontrib><creatorcontrib>Kim, Yong-Hun</creatorcontrib><creatorcontrib>Kim, Sooyoung</creatorcontrib><creatorcontrib>Park, Wansoo</creatorcontrib><creatorcontrib>Kim, Seok-Jung</creatorcontrib><creatorcontrib>Lee, Chan-Yong</creatorcontrib><creatorcontrib>Lee, Seungseob</creatorcontrib><creatorcontrib>Park, Tae-Hoon</creatorcontrib><creatorcontrib>Oh, Chi-Sung</creatorcontrib><creatorcontrib>Ban, Hyodong</creatorcontrib><creatorcontrib>Ko, Hyungjong</creatorcontrib><creatorcontrib>Song, Hoyoung</creatorcontrib><creatorcontrib>Oh, Tae-Young</creatorcontrib><creatorcontrib>Hwang, Sang-Joon</creatorcontrib><creatorcontrib>Oh, Kyung-Suk</creatorcontrib><creatorcontrib>Choi, Jung-Hwan</creatorcontrib><creatorcontrib>Lee, Jooyoung</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005–Present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE/IET Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE journal of solid-state circuits</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Lee, Daewoong</au><au>Baek, Jaehyeok</au><au>Kwon, Hye-Jung</au><au>Kwon, Dae-Hyun</au><au>Cho, Chulhee</au><au>Kim, Sang-Hoon</au><au>An, Donggun</au><au>Chang, Chulsoon</au><au>Lim, Unhak</au><au>Im, Jiyeon</au><au>Sung, Wonju</au><au>Kim, Hye-Ran</au><au>Park, Sun-Young</au><au>Kim, Hyoung-Joo</au><au>Seol, Hoseok</au><au>Kim, Juhwan</au><au>Shin, Jungbum</au><au>Kang, Gil-Young</au><au>Kim, Yong-Hun</au><au>Kim, Sooyoung</au><au>Park, Wansoo</au><au>Kim, Seok-Jung</au><au>Lee, Chan-Yong</au><au>Lee, Seungseob</au><au>Park, Tae-Hoon</au><au>Oh, Chi-Sung</au><au>Ban, Hyodong</au><au>Ko, Hyungjong</au><au>Song, Hoyoung</au><au>Oh, Tae-Young</au><au>Hwang, Sang-Joon</au><au>Oh, Kyung-Suk</au><au>Choi, Jung-Hwan</au><au>Lee, Jooyoung</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A 16-Gb T-Coil-Based GDDR6 DRAM With Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus Achieving 27-Gb/s/Pin in NRZ</atitle><jtitle>IEEE journal of solid-state circuits</jtitle><stitle>JSSC</stitle><date>2023-01-01</date><risdate>2023</risdate><volume>58</volume><issue>1</issue><spage>279</spage><epage>290</epage><pages>279-290</pages><issn>0018-9200</issn><eissn>1558-173X</eissn><coden>IJSCBC</coden><abstract>This article introduces a 16-Gb T-coil-based graphics double-data-rate 6 (GDDR6) dynamic random access memory (DRAM) with merged-multiplexer (MUX) transmitter (TX), optimized data clock (WCK) operation to enhance I/O bandwidth. T-coil is implemented for the first time in a DRAM process. Moreover, an alternative-data-bus (ADB) is employed to solve the frequency limit of the data bus. The proposed T-coil-based GDDR6 DRAM achieves 27 Gb/s/pin with 1.35 V in a DRAM process.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/JSSC.2022.3222203</doi><tpages>12</tpages><orcidid>https://orcid.org/0000-0001-8703-2627</orcidid><orcidid>https://orcid.org/0000-0002-9379-7746</orcidid><orcidid>https://orcid.org/0000-0003-4651-2434</orcidid><orcidid>https://orcid.org/0000-0003-3507-2613</orcidid><orcidid>https://orcid.org/0000-0002-3611-4734</orcidid></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 0018-9200 |
| ispartof | IEEE journal of solid-state circuits, 2023-01, Vol.58 (1), p.279-290 |
| issn | 0018-9200 1558-173X |
| language | eng |
| recordid | cdi_proquest_journals_2758722715 |
| source | IEEE/IET Electronic Library (IEL) |
| subjects | Alternative-data-bus (ADB) Bandwidth Clocks Coils data clock (WCK) Dynamic random access memory Graphics graphics double-data-rate 6 (GDDR6) graphics dynamic random access memory (DRAM) high-speed memory Load modeling merged-multiplexer (MUX) transmitter (TX) Metals quad-skew training Random access memory reference impedance (ZQ) calibration Resistance T-coil wireline transceiver |
| title | A 16-Gb T-Coil-Based GDDR6 DRAM With Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus Achieving 27-Gb/s/Pin in NRZ |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-07T17%3A58%3A07IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_RIE&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=A%2016-Gb%20T-Coil-Based%20GDDR6%20DRAM%20With%20Merged-MUX%20TX,%20Optimized%20WCK%20Operation,%20and%20Alternative-Data-Bus%20Achieving%2027-Gb/s/Pin%20in%20NRZ&rft.jtitle=IEEE%20journal%20of%20solid-state%20circuits&rft.au=Lee,%20Daewoong&rft.date=2023-01-01&rft.volume=58&rft.issue=1&rft.spage=279&rft.epage=290&rft.pages=279-290&rft.issn=0018-9200&rft.eissn=1558-173X&rft.coden=IJSCBC&rft_id=info:doi/10.1109/JSSC.2022.3222203&rft_dat=%3Cproquest_RIE%3E2758722715%3C/proquest_RIE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=2758722715&rft_id=info:pmid/&rft_ieee_id=9968075&rfr_iscdi=true |